AD9361 interface timing with FIR filter and 61.44MSPS sample rate

Can you provide some context as to what this comment means and what the limitations are? https://github.com/analogdevicesinc/no-OS/blob/master/drivers/rf-transceiver/ad9361/ad9361.c#L4669-L4674

 

Where does that timing failure manifest itself?  Is it something that can be fixed through Clock/Data delay tuning?  Is it exacerbated if we use 2R2T mode?