spi_init error using AD7134_EVAL board with zedboard running no-os

Thanks.  Now I do have the code running properly and SPI seems to be happy.  However, my output is all 0.0V. 

The very first time after power cycling the board:

2nd run after power up:

3rd run:

4th run:

Hello Vick,

Did you connect anything at the input of the ADC channels so you can actually see if the samples are corresponding to the input voltage values? (at least for the first run after power cycle)

Also, are you re-programming the FPGA before each run of the code?

Regards,

Antoniu

I think there are still issues with this no-os code, related to SPI.  I have scope probes attached to SCLK, SDO, and SDI at the TP locations on the AD7134 boards. I'm probing TP86 (SCLK), TP64 (SDO), TP59 (SDI) right at the FMC connector.

For these two init instructions:

    ret = ad713x_init(&ad713x_dev_1, &ad713x_init_param_1);
    if (ret != SUCCESS)
        return FAILURE;
    mdelay(1000);
    ad713x_init_param_2.spi_common_dev = ad713x_dev_1->spi_desc;
    ret = ad713x_init(&ad713x_dev_2, &ad713x_init_param_2);
    if (ret != SUCCESS)
        return FAILURE;

I see

For this instruction:

    ret = spi_engine_offload_transfer(spi_eng_desc, spi_engine_offload_message,
                      (AD7134_FMC_CH_NO * AD7134_FMC_SAMPLE_NO));
    if (ret != SUCCESS)

I see nothing on the SPI signals, even though the return is SUCCESS.

I believe this is why my data is all 0x0.

Thanks for your help.

Did you connect anything at the input of the ADC channels so you can actually see if the samples are corresponding to the input voltage values? (at least for the first run after power cycle)

Yes, I have 1V DC attached to Channel 1.

Also, are you re-programming the FPGA before each run of the code?

Yes, I just tried that again and the result is still the same;  all 0x0 on the returned data. 

After discussing with the local FAE, I discovered that the ADC data will actually be transferred over the DOUT signals (not the SPI bus).   I connected the following signals to my scope to monitor them during the code execution:  DCLK on TP66, ODR on TP67, DOUT0_1 on TP68, DOUT0_2 on TP64.

None of these signals are changing state during the code execution.

1) Am I probing the right signals?

2) What might be causing this issue?

Thanks.

I found my problem.  The missing piece of the puzzle is the jumpers JP14 - JP17.  The user guide is not real clear on these and the boards are delivered in a non-operational mode.  JP14-16 are all installed, meaning all GND.  The schematic shows JP14 and JP16 should be open.  Once I removed JP14 and JP16, I started getting data that looks right.

So, in summary these are the issues I've discovered with the AD7134_EVAL board so far:

1)  This board will not mate properly with a zedboard because of an interference issue;  an adapter cable will be required

2)  The no-os code originally supplied came with some coding errors;  still waiting for the merged fix on the master branch

3)  The board is shipped with the JP14-JP17 jumpers all installed;  this mode results in a non-operational board;  JP14 and JP16 must be removed for one of the operational modes.  The users guide is not really explicit regarding these jumpers.