Hi,I am using the hdl release 'hdl_2019_r1'. And I am using the project in zc706 and EVAL-ADRV9008/9.
I am using no-os project for xilinx sdk , it works well . I found that the DAC data could be sourced from the external DDR at ADRV9009 HDL Reference Design.
How to source DAC data from the external DDR with adrv9009 reference design? Seems it is the internal DDS by default.
Help me please.. Give me some clues, thanks.
Hi , I found this 'DAC Channel' things from Generic AXI DAC IP core. I cut a picture of DAC Channel's regmap here.
Can i set the DAC channel for adrv9009 rely on the information in the picture?
Otherwise there is a file 'hdl_2019_r1/projects/adrv9009/zc706/adrv9009_zc706.srcs/sources_1/bd/system/common/up_dac_channel.v' ,there is a parameter named 'DDS_DISABLE' in the file,but the file is read-only. I am so confused..
Maybe this parameter should be set to '0x01' if i wanna use the external ddr to source the DAC data?
Am i supposed to change it or not ? Can u or someone else explain it? Thanks a lot.
Hi , I found this 'DAC Channel' things from Generic AXI DAC IP core. I cut a picture of DAC Channel's regmap here.
Can i set the DAC channel for adrv9009 rely on the information in the picture?
Otherwise there is a file 'hdl_2019_r1/projects/adrv9009/zc706/adrv9009_zc706.srcs/sources_1/bd/system/common/up_dac_channel.v' ,there is a parameter named 'DDS_DISABLE' in the file,but the file is read-only. I am so confused..
Maybe this parameter should be set to '0x01' if i wanna use the external ddr to source the DAC data?
Am i supposed to change it or not ? Can u or someone else explain it? Thanks a lot.
