AD9371-ZC706 No-OS-master application generation

Hi ADI.

     I'm trying to do some thing with AD9371 and zc706. The version of the Vivado is 2019.1.  

      ADRV9371ZC706

     What I did is as follow:

    1、I builded the HDL project according to the guide (https://github.com/analogdevicesinc/hdl, hdl_2019_r2 )and got the file system_top.hdf in the sdk.

          hdl

    2、I builded the no-OS-mastar project according to the guide (https://github.com/analogdevicesinc/no-OS and https://wiki.analog.com/resources/no-os/build) and got the elf file.

      elf

    3、I ran the command “make run” to upload the binary to target. The result of the UART terminal is only “Please wait...”. I found the MYKONOS_initialize failed in the headless.c file. It seems

that the program stops when it runs to MYKONOS_setSpiSettings in the mykonos.c file.

makerun

uart terminal

headless

setSpiSettings

Is there some problems with my operation? How can I successfully run this application?

Thank you!

Top Replies

    •  Analog Employees 
    Apr 13, 2021 +1 verified

    Hello Lao wang,

    Based on our previous discussions in other threads I suppose you have solved your issue.

    Although I checked again the no-OS master branch with 2019_r2 hdl and the application runs fine:

  • 0
    •  Analog Employees 
    on Mar 27, 2021 8:34 AM

    Hi,

    Can you try again with the same .hdf and same tools, but using the no-OS "master" branch?

    Thanks,
    Dragos

  • Hi Dragos.

    The branch of no-OS I used is the master. Are there any other questions here?

    Think you.

  • 0
    •  Analog Employees 
    on Mar 29, 2021 2:51 PM in reply to Lao wang

    No, we need to do a test too. We'll let you know the result.

    Thanks,
    Dragos

  • +1
    •  Analog Employees 
    on Apr 13, 2021 2:17 PM

    Hello ,

    Based on our previous discussions in other threads I suppose you have solved your issue.

    Although I checked again the no-OS master branch with 2019_r2 hdl and the application runs fine:

    Please wait...
    rx_clkgen: MMCM-PLL locked (122880000 Hz)
    tx_clkgen: MMCM-PLL locked (122880000 Hz)
    rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Calibrations completed successfully
    tx_adxcvr: OK (4915200 kHz)
    rx_adxcvr: OK (4915200 kHz)
    rx_os_adxcvr: OK (4915200 kHz)
    rx_jesd status:
        Link is enabled
        Measured Link Clock: 122.887 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 3.840 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
    rx_jesd lane 0 status:
    Errors: 1
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 76 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x47, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
    rx_jesd lane 1 status:
    Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 75 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x48, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
    tx_jesd status:
        Link is enabled
        Measured Link Clock: 122.887 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 7.680 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
    rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 122.887 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 7.680 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
    rx_os_jesd lane 0 status:
    Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 7 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x43, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
    rx_os_jesd lane 1 status:
    Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 6 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x44, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
    tx_dac: Successfully initialized (245773315 Hz)
    rx_adc: Successfully initialized (122886657 Hz)
    rx_obs_adc: Successfully initialized (245773315 Hz)
    Done

    Closing this thread.