ADRV9008-1 + ADRV9008-2 + ZCU102 REFERENCE DESIGN HELP

Hello,

Are you using Linux or No-OS ? 

In my opinion, the two boards can be brought up sequentially, as if they are the only ones on the ZCU102, so the code you've used for a single ADRV9008-2 should work on this project, with the SPI/GPIOs adjusted to reflect the new design. I suppose, you'll need also GPIOs, not only SPI to each board. If the two boards need common clocking, or have other synchronization requirements, things may be more complex.

Regards,

Adrian

Waiting for your reply...

Hello Siddharth,

Assuming you have ADRV9008-1 on HPC0 and ADRV9008-2 on HPC1, starting with the default reference design you should have all things needed for ADRV9008-2 (SPI and GPIO).

When adding ADRV9008-1, you need to clone the same SPI and GPIO connections (you'll need a connection to AD9528 and another to ADRV9008-1). Of course, the same goes for the JESD204 path.

After the HDL is create, the addition of ADRV9008-1 should not interfere with ADRV9008-2, meaning the same software should work to bring the device up. Is this the case ?

Regards,

Adrian

Hi Adrian

Thanks for the response.

I would like to clarify the exact details what we want to do.

Our custom board is almost similar to ADRV9009-ZU11EG hardware design.

We have  ADRV9008-1(1)+ADRV9008-2(1)+AD9528(In place of HMC7044)+Xilinx MPSoC all in same board.

Now we are trying to replicate the above scenario using ZCU102+ADRV9008-1(HPC0)+ADRV9008-2(HPC1).

In order to replicate this hardware wise,we will use only one of AD9528(lets say HPC0) and drive the  dev clock and sysref of AD on HPC1 using cables.

"When adding ADRV9008-1, you need to clone the same SPI and GPIO connections (you'll need a connection to AD9528 and another to ADRV9008-1). Of course, the same goes for the JESD204 path."

Do you mean 2 AD9528 on ADRV9008-1 and ADRV9008-2 or only 1 AD9528 (either from ADRV9008-2 or ADRV9008-1)? 1 AD9528 will be like common clock source for SoC,ADRV9008-1 and ADRV9008-2.

If its 2 AD9528,then SPI_MISO corresponding to 2 AD9528 will be difficult to make since we have only 3 CS.

"After the HDL is create, the addition of ADRV9008-1 should not interfere with ADRV9008-2, meaning the same software should work to bring the device up. Is this the case ?"

 Yes exactly same software should work to bring the device up.

Regards

Siddharth

Hello Siddharth, 

The problem is that the HPC0 and HPC1 are connected to different transceiver banks, which are not adjoined, so they need their own reference clock. On our ADRV9009-ZU11EG, this is not a problem, as they are connected to adjoined banks.

Regarding SPI, i was thinking to use SPI0 to connect to HPC0 evaluation board ICs and SPI 1 to connect to HPC1 evaluation board ICs(or vice versa), so you should have 3 CS per SPI, but given that you have 6 CS, should be enough.

I know there were customers that synchronized two ADRV9009 evaluation boards on ZCU102 by synchronizing the AD9528, but I don't know exactly the details on how to do that. This would bring the evaluation system closer to your final design.

Regards,

Adrian

Hello Adrian,

Thanks for the prompt response.

"The problem is that the HPC0 and HPC1 are connected to different transceiver banks, which are not adjoined, so they need their own reference clock. On our ADRV9009-ZU11EG, this is not a problem, as they are connected to adjoined banks."

 So for our custom board,since ADC and DAC are connected to adjacent banks,we should be able to use ADRV9009-ZU11EG HDL reference design but in software we need to take into account of AD9528 in place of HMC7044 and ADRV9008-2 and ADRV9008-1 in place of 2 ADRV9009. We will be needing your help in configuring the same in no-os in near future.

"Regarding SPI, i was thinking to use SPI0 to connect to HPC0 evaluation board ICs and SPI 1 to connect to HPC1 evaluation board ICs(or vice versa), so you should have 3 CS per SPI, but given that you have 6 CS, should be enough."

As of now we would like to configure the way you have described using 2 SPIs.Please guide us what changes needs to be done in no-os software that is available for ADRV9009 so that we can configure ADRV9008-1+ADRV9008-2.

 FYI: Once again mentioning that I tried to independently interface ADRV9008-1 with ZCU102 by using the same code  which is there for ADRV9009 with few changes like we made TX_Enable as OFF and RX_Enable to be ON,we disabled the DAC initilazation part from Transport to PHY layer including clock  also, but its popping the following error: ERROR:247:TALISE_waitArmCmdStatus() failed due to thrown ARM error.ARM time out error:TALISE_waitInitCals() failed.

Regards

Siddharth

Sid@123 said:

So for our custom board,since ADC and DAC are connected to adjacent banks,we should be able to use ADRV9009-ZU11EG HDL reference design but in software we need to take into account of AD9528 in place of HMC7044 and ADRV9008-2 and ADRV9008-1 in place of 2 ADRV9009. We will be needing your help in configuring the same in no-os in near future.

That's correct. You could also probably squeeze both ADRVs in a single transceiver bank, if the application suits that.

Regarding the no-os configuration, I will move the question to the appropriate forum and somebody from that group can give you specific instructions.

Regards,

Adrian

Sid@123 said:

So for our custom board,since ADC and DAC are connected to adjacent banks,we should be able to use ADRV9009-ZU11EG HDL reference design but in software we need to take into account of AD9528 in place of HMC7044 and ADRV9008-2 and ADRV9008-1 in place of 2 ADRV9009. We will be needing your help in configuring the same in no-os in near future.

That's correct. You could also probably squeeze both ADRVs in a single transceiver bank, if the application suits that.

Regarding the no-os configuration, I will move the question to the appropriate forum and somebody from that group can give you specific instructions.

Regards,

Adrian

Moved to No-OS forum

Hi Adrian,

Now we want to configure "as discussed earlier in this thread" ADRV9008-1 on HPC0 and ADRV9008-2 on HPC1 at a time. As advised by you, we used SPI0 for HPC0 and SPI1 for HPC1.Similarly for gpio lines we mapped to both HPC's. Also pin planning is being done for both HPC corresponding lines towards FPGA. Now regarding JESD lines,since MGT banks corresponding to HPC0 and HPC1 are not adjoined,we need to replicate GTHE4 XCVR block in block design of reference HDL design.Please guide us in, how to add another GTHE4 XCVR block for the other HPC and what all changes needs to be done so that our HDL design for both HPC is ready.

Regards

Siddharth

Hello Siddharth,

Ultimately you'll need two util_adxcvr blocks, one for each HPC, which will either connect one RX (2 RX lanes) or one TX and one ORx( 4 TX lanes and 2 RX lanes) and reconnect the data link layers to the coresponding util_adxcvr. 

As an intermediary step you could copy the whole data path for JESD204 so you'll have support for two ADRV9009s, with the correct pinout and reference clocks (for one path pinout for HPC0 and for the other HPC1) and afterwards remove the pieces that are not needed.

Do you have a github repository with your HDL changes ? I could take a look and give specific pointers.

Regards,

Adrian

Hello Adrian,

I replicated only util_adxcvr part as my requirement is ADRV9008-1 on 1 hpc and ADRV9008-2 on other hpc. Also i cloned spi and gpio connections as advised by you. In implemented design, tx and rx jesd data lines are placed in respective banks corresponding to hpc0 and hpc1.

Before validating whole setup on hardware, with this bitstream what i hv generated now,is it ok to connect only adrv9008-2 on hp1 and check whether its working fine and then similarly for only adrv9008-1 on hp0 and then go for combined setup with changes in no-os code that caters both adrv9008.

Regards

Siddharth

Hello,

Yes, validating independently should be good steps in validating the whole design.

Regards,

Adrian

Hello Adrian,

 I validated independently ADRV9008-2 on hp1 and ADRV9008-1 on hp0 using bitstream(combined logic hp0 and hp1) and in both the cases device is in data mode which means its all fine.

But 1 observations:

I routed spi0 to hp0 in hdl design and in no-os platform, device_id is set to 0 and gpios for adrv9009_resetb and ad9528_resetb has been set with an offset of 78. Next when I checked ADRV9008-2 on hp1,i only changed device id to 1 as spi1 is mapped in hdl but didn't change the gpios value for ADRV9008-2 and AD9528 resets in parameters.h, then it should not have been configured. But its configured successfully with data mode. Also when I gave the required gpio values its working in data mode.

Regards

Siddharth 

Hello Adrian!!

Waiting for your reply...

If this part what I asked is clear,then I can focus on configuring both hp0 and hp1 sequentially in baremetal.

Thanks n regards 

Siddharth

Hello Siddharth,

Do you have a branch with the full design or a block diagram ?

I wasn't sure if it was a question or just an observation, but indeed it seems strange, but I cannot say why it happen from the description above.

Regards,

Adrian

Regarding the software changes you did, maybe somebody from the software group may add additional comments, but I suppose they would also need additional clarifications with the exact changes.

Hello Adrian!!!

Thanks so much for all the guidance regarding HDL. Also i would like to thank buha for helping in getting no-os project with code segregation between ADRV9008-1 and ADRV9008-2. This was really helpful while doing no-os for both ADC and DAC together.

Now i am able to configure both ADRV9008-1+AD9528 on HPC0 and ADRV9008-2+AD9528 on HPC1 simultaneously.

It took much time as i was not continuously working on it.

Also with respect to last question what i asked,i think i got the clarity now. My doubt was, without proper gpio assignment for reset signal in HPC0,still ADC was getting configured. Actually it can be configured what i observed,only problem will be when we want to re run the system debugger for configuration,ADC wont configure.It will fail in Talise_initialize. We have to repower the board in this case. Once i did the proper assignment of gpio,this was solved.

I have to do a RF-loop back test and will ask for your support if required.

Thanks & Regards

Siddharth