AD9375 Evaluation - Register mismatch error with 2019_R1 release source code of PS and PL

We are working on testing JESD with ADRV9375 evaluation board. The source code is taken from the below repository (Using 2019_R1, with Vivado 2018.3)

https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r1

https://github.com/analogdevicesinc/no-OS/tree/2019_R1/projects/ad9371/src

We are able to generate .hdf from Vivado 2018.3 using the procedure mentioned in the link below.

https://wiki.analog.com/resources/fpga/docs/build

And in the process of making executable for with Xilinx SDK 2018.3 using the procedure mention in the link below.

https://wiki.analog.com/resources/eval/user-guides/mykonos/no-os-setup#push_data_intoout_of_the_ad9371ad9375

In the process we are getting stuck with the error in register mapping. Please see the snap below FYR.

This variable not covered in the xplatform.h file generated. Need support on the solving this error.

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