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How to enable external clock 10MHZ for AD9361-z7035 using no-os drivers

Hello Support team,

We use the picozed hardware(AD9361-z7035 with ADRV1-CRR-BOB). We use the latest release of no-os drivers. Our application needs 10MHz external reference clock. AD9361-z7035 hardware takes external clock signal via one SMA connector which goes to a MUX.By default the MUX is selected to give the 40MHz reference available on board to Ad9361. To enable external reference, we made the following changes in the structure "default_init_param" in main.c of no-OS driver for AD9361-z7035(Latest release).

/* Reference Clock */

40000000UL, //reference_clk_rate /*

Reference Clock Control */

1, //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable

CLKOUT_DISABLE, //clk_output_mode_select *** adi,clk-output-mode-select

We found that after doing the above setting also, when we checked the o/p by giving TX LO frequency it is showing the signals whether i enable or disable the external clock. Please guide us how to enable and use the external clock of 10 MHz as AD9361 clock.

Thank you

Parents
  • xo_disable_use_ext_refclk_enable controls in the clock input circuit inside the chip. It basically disables the internal oscillators which requires a XTAL, and you directly need to feed a clock into the pad. The external mux is controlled via GPIO controlled via the ZYNQ. Please check your schematics. 

  • Hello,

    Thank you for your reply.

    I did the same thing which you mentioned in above comment but still I am getting the set TX LO frequency signals whether I enable or disable the external clock. I have another questions please find the below questions.

    1). I want to enable external reference clock 10MHZ and i am using ADRV1CRR-BOB with AD9361. What settings I need to modify by using no-os drivers?

    2). If I want to use Linux drivers for same then how should I do it?

    3). When should I have to give external clock? before uploading the program into the target board or after it?

    Waiting for your reply.

    Thank you.

  • Hello

    As per our application we have to use 10MHZ external reference clock and we are using ADRV1CRR-BOB with AD9361. And we are trying to enable external reference clock by using no-os drivers (latest release).

    We made the below below settings in the no-os code.

    1. define the ADI_RF_SOM

    2. default_init_param.reference_clk_rate = 40000000UL;

    3. default_init_param.xo_disable_use_ext_refclk_enable = 1;

    4. ad9361_set_tx_lo_freq(ad9361_phy, 2250000000);

    After made this changes in no-os code, we created test setup and we program the no-os code into the target board and initializes it. We have set TX LO frequency as 2250 MHZ. Please find the below mentioned points.

    1. When we test the no-os code with internal TCXO with 40MHZ reference clock rate it gives the correct LO frequency. Please find the below attached picture for same.

                        figure 1: internal_40mhz_2250_tx2a

    2. When we test the no-os code with disabling internal TCXO with 40MHZ reference clock rate and set the external reference clock as 50MHZ and not give the any external reference clock then it also show the LO frequency signal and it shows the random LO frequency. Please find the below attached picture for same.

                      figure : 2 internal_tcxo_disable_code_dump_w_o_external_given_set_50mhz

    3. When we test the no-os code with disabling internal TCXO with 40MHZ reference clock rate and set the external reference clock as 50MHZ and give the external reference clock 50MHZ from outside with 1-1.2vpp then it also show the LO frequency and it's give random frequency. Please find the attached picture for same.

                  figure 3: int_disable_external_50mhz_given_1p2vp-p

    Kindly guide us for the below mentioned points.

    1). Is there any other method to test the same?

    2). As mentioned above it gives the same output if we disable the external reference clock or not please guide us how could be disable the internal TCXO using no-os drivers?

    3). When we to apply reference clock rate as 10MHZ, 20MHZ or 30MHZ it shows the below mentioned error. Kindly guide us how to solve it.

    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x247, 0x2)
    Calibration TIMEOUT (0x287, 0x2)
    Calibration TIMEOUT (0x247, 0x2)
    cf-ad9361-lpc: Successfully initialized (224211120 Hz)
    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x5E, 0x80)
    SAMPL CLK: 61440000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # # # # # # # # # # # # # # #
    ad9361_dig_tune_delay: Tuning RX FAILED!
    ad9361_init : AD936x initialization error

    Please reply as soon as possible as our project is delayed because of the external clock issue.

    Waiting for your reply.

    Thank you.

      

  • Did you change the MUX GPIO to select the external reference?

  • Hi

    Where should i change the MUX GPIO to select the external reference in no-os code?

  • You need to add such code yourself. gpio_get(), gpio_direction_output(), 

    Add it to main() before the ad9361_init(). The GPIO number is 105.

  • Have a look here:

    ADRV9361-Z7035 User Guide - Electrical Specifications [Analog Devices Wiki]
    hdl/adrv9361z7035_constr.xdc at master · analogdevicesinc/hdl (github.com)
    hdl/system_top.v at master · analogdevicesinc/hdl (github.com)

    So, according to system_top.v, the offset of the gpio_clksel is 51, but 54 has to added to that number (Zynq has 4 banks of GPIOs (32-bit, 22-bit, 32-bit, 32-bit): banks 0 and 1 are for the MIO pins (54) and banks 2 and 3 are for the EMIO pins (64)).

    Thanks,
    Dragos

  • Hello

    Thank you for your reply.

    Please find the below mentioned code.

    #define GPIO_MUX_CLKSEL 105

    #if defined FMCOMMS5 || defined ADI_RF_SOM || defined ADI_RF_SOM_CMOS
    gpio_get(GPIO_MUX_CLKSEL,1);
    gpio_direction_output(GPIO_MUX_CLKSEL,GPIO_HIGH);
    default_init_param.reference_clk_rate = 10000000UL;
    default_init_param.xo_disable_use_ext_refclk_enable = 1;
    #endif

    Is this correct or i am doing something wrong? Please guide me.

    Thank you.

  • It doesn't look right: https://github.com/analogdevicesinc/no-OS/blob/master/include/gpio.h#L136-L137

    gpio_get() needs a struct gpio_desc and a struct gpio_init_param ,so, you need something like:

       struct xil_gpio_init_param xil_gpio_param = {
          .type = GPIO_PS,
          .device_id = GPIO_DEVICE_ID
       };

       const struct gpio_init_param clksel_init = {
          .number = 105,
          .platform_ops = &xil_gpio_platform_ops,
          .extra = &xil_gpio_param
       };

       struct gpio_desc *gpio_clksel;

    Thanks,
    Dragos

  • Hello

    Thank you for your help.

    As you suggested i made the changes in the no-os code. Which is mentioned below.

    struct xil_gpio_init_param xil_gpio_param = {
    #ifdef PLATFORM_MB
    .type = GPIO_PL,
    #else
    .type = GPIO_PS,
    #endif
    .device_id = GPIO_DEVICE_ID
    };
    #endif

    const struct gpio_init_param clksel_init = {
    .number = 105,
    .platform_ops = &xil_gpio_platform_ops,
    .extra = &xil_gpio_param
    };

    struct gpio_desc *gpio_clksel;

    #if defined FMCOMMS5 || defined ADI_RF_SOM || defined ADI_RF_SOM_CMOS
    gpio_get(&gpio_clksel,&clksel_init);
    gpio_direction_output(gpio_clksel,GPIO_HIGH);
    default_init_param.reference_clk_rate = 50000000UL;
    default_init_param.xo_disable_use_ext_refclk_enable = 1;
    #endif

    Still i am getting the same output as mentioned in previous reply. 

    Kindly guide us if i am missing something or doing anything wrong.

    Thank you.

  • Can you show us how the ADG772's output looks like (signal 9361_XTAL)?

    Thanks,
    Dragos

  • Hello

    Please find the below attached ADG772's output.

    1). ADG772's output with internal TCXO 40 MHZ

    2). ADG772's output with external clock reference 50MHZ

     

    3). ADG772's output in time domain

    As you shown in the attached picture with the below setting in the no-os code we are unable to disable the internal clock.

    struct xil_gpio_init_param xil_gpio_param = {
    #ifdef PLATFORM_MB
    .type = GPIO_PL,
    #else
    .type = GPIO_PS,
    #endif
    .device_id = GPIO_DEVICE_ID
    };
    #endif

    const struct gpio_init_param clksel_init = {
    .number = 105,
    .platform_ops = &xil_gpio_platform_ops,
    .extra = &xil_gpio_param
    };

    struct gpio_desc *gpio_clksel;

    #if defined FMCOMMS5 || defined ADI_RF_SOM || defined ADI_RF_SOM_CMOS
    gpio_get(&gpio_clksel,&clksel_init);
    gpio_direction_output(gpio_clksel,GPIO_HIGH);
    default_init_param.reference_clk_rate = 50000000UL;
    default_init_param.xo_disable_use_ext_refclk_enable = 1;
    #endif

    Kindly guide us and reply as soon as possible.

    Thank you.

Reply
  • Hello

    Please find the below attached ADG772's output.

    1). ADG772's output with internal TCXO 40 MHZ

    2). ADG772's output with external clock reference 50MHZ

     

    3). ADG772's output in time domain

    As you shown in the attached picture with the below setting in the no-os code we are unable to disable the internal clock.

    struct xil_gpio_init_param xil_gpio_param = {
    #ifdef PLATFORM_MB
    .type = GPIO_PL,
    #else
    .type = GPIO_PS,
    #endif
    .device_id = GPIO_DEVICE_ID
    };
    #endif

    const struct gpio_init_param clksel_init = {
    .number = 105,
    .platform_ops = &xil_gpio_platform_ops,
    .extra = &xil_gpio_param
    };

    struct gpio_desc *gpio_clksel;

    #if defined FMCOMMS5 || defined ADI_RF_SOM || defined ADI_RF_SOM_CMOS
    gpio_get(&gpio_clksel,&clksel_init);
    gpio_direction_output(gpio_clksel,GPIO_HIGH);
    default_init_param.reference_clk_rate = 50000000UL;
    default_init_param.xo_disable_use_ext_refclk_enable = 1;
    #endif

    Kindly guide us and reply as soon as possible.

    Thank you.

Children
  • Why do you set this GPIO high? From my understanding, for disabling the onboard reference, you should set it low. IO_00_34_AD9361_CLKSEL is pulled up to VDD through R55, so even unconfigured, its value will be high.

    Please measure the IO_00_34_AD9361_CLKSEL signal in both situations:
       - gpio_direction_output(gpio_clksel,GPIO_LOW)

       - gpio_direction_output(gpio_clksel,GPIO_HIGH)

    Thanks,
    Dragos

  • Hii

    When I tested the code, I set the GPIO as LOW but I am getting the below error.

    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x247, 0x2)
    Calibration TIMEOUT (0x287, 0x2)
    Calibration TIMEOUT (0x247, 0x2)
    cf-ad9361-lpc: Successfully initialized (167050170 Hz)
    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x5E, 0x80)
    SAMPL CLK: 61440000 tuning: RX
      0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # # # # # # # # # # # # # # #
    ad9361_dig_tune_delay: Tuning RX FAILED!
    ad9361_init : AD936x initialization error

    How should I solve it? Kindly provide guidance.

    Thank you.

  • Please measure the IO_00_34_AD9361_CLKSEL voltage.

    Thanks,
    Dragos

  • Hii

    You can see the value of voltage for IO_00_34_AD9361_CLKSEL in the below attached picture.

          Figure 1: value of voltage for IO_00_34_AD9361_CLKSEL

    Please find the below attached screenshot, when I set the GPIO as LOW.

    1). For 10MHZ external clock

    2). Time domain for 10MHZ external clock

    3). For 50MHZ external clock

    4). Time domain for 30MHZ external clock

    As you shown in the attached picture when the frequency is low the power level is also low.

    We give the 1-1.2vpp from the outside.

    We still getting the above mentioned error by setting the GPIO value as LOW.

    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x247, 0x2)
    Calibration TIMEOUT (0x287, 0x2)
    Calibration TIMEOUT (0x247, 0x2)
    cf-ad9361-lpc: Successfully initialized (167050170 Hz)
    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x5E, 0x80)
    SAMPL CLK: 61440000 tuning: RX
      0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # # # # # # # # # # # # # # #
    ad9361_dig_tune_delay: Tuning RX FAILED!
    ad9361_init : AD936x initialization error

    Please provide guidance.

    Waiting for your reply.

    Thank you.

  • Your "Figure 1: value of voltage for IO_00_34_AD9361_CLKSEL" seems to show the 9361_XTAL signal, not the IO_00_34_AD9361_CLKSEL one.

    Anyway, your reference doesn't look good to me - try to provide something similar to the onboard reference. Check the AD9361's datasheet recommendation related to the reference clock.

    Dragos

  • Hello

    I already attached the onboard reference output signal of ADG772 in the previous reply. Please find the below attached picture for your reference.

    1). ADG772's output with internal TCXO 40 MHZ

    Kindly help us to solve the calibration timeout error which I mentioned in the previous reply.

    When I set the value of GPIO as LOW then it occurred.

    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x247, 0x2)
    Calibration TIMEOUT (0x287, 0x2)
    Calibration TIMEOUT (0x247, 0x2)
    cf-ad9361-lpc: Successfully initialized (167050170 Hz)
    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x5E, 0x80)
    Calibration TIMEOUT (0x5E, 0x80)
    SAMPL CLK: 61440000 tuning: RX
      0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # # # # # # # # # # # # # # #
    ad9361_dig_tune_delay: Tuning RX FAILED!
    ad9361_init : AD936x initialization error

    Thank you.

  • Can you try using 20MHz? Like I said before 10MHz can be problematic.

  • Yes I tried 20MHZ and also tried 30MHZ but for both I am getting calibration timeout error.

  • Try to increase the voltage swing - looks like it's not even close to 1.3Vpp

  • Is there any relation between voltage swing and calibration timeout error?