AD9361 No-OS API about "agc_inner_thresh_high" ?

Yes, 10 is the default value for this agc high  threshold. Yes the description of the registers are correct(if bit D7 is enabled, then digital saturation will cause a gain decrease).

Hi srimoyi - san,

Thank you for reply.

We are still confused.

agc_inner_thresh_high ; 0x101[D6:D0] 10 default

Which command is it? ; 0x101[D7]  0 default ?

Best regards,

sss

Moving to no-os forum for details about this feature.

Hello,

Apologies for the delayed response.

Are you confused about why there are two defaults mentioned? If so, it's likely because the first one refers to the least significant 7 bits of the 0x101 register and the second refers to the most significant one. That means that by default AGC lock level is disabled (bit D7) and the lock level is 0x10 (bits D6 - D0).

Does this answer your question?

Regards,
Andrei

Hi Andrei- san,

Thank you for reply.

Please let me know if my understanding is correct.

agc_inner_thresh_high ; 0x101[D7] 0 default , 0x101[D6:D0] 10 default ; 

 xyyy yyyy ; x=AGC lock level enable/disabled , y= lock level set

Best regards,

sss

This is correct.

Regards,
Andrei