AD9009 reference design using stratix 10


we are looking for some suggestion about AD9009 reference design using stratix 10。

we found that there exist a project naming hdl/projects/adrv9009/s10soc/ in hdl github, has it been verified?  Does it support no-OS or linux?

we noticed that, in quartus 19.2 Pro, s10 fpll fpga ip won't support dynamic configuration,  so when we use hdl branch qpro_s10  as our hardware project, and use no-OS 2019r1 as our software project, the initialization of fpll is not correct, the log screen is below:

so how should we modify the hdl project and no-OS nios project?

or Is there a roadmap for s10 device support?