AD9371 ADC Capture Example Script

Hi Hasan,

The data is being captured at this line https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/app/headless.c#L1112

If you wan to print the data, you can add the following lines to your code:

    axi_dmac_transfer(rx_dmac,
                    DDR_MEM_BASEADDR + 0x800000,
                    16384 * 8);
#ifndef ALTERA_PLATFORM
	Xil_DCacheInvalidateRange(DDR_MEM_BASEADDR + 0x800000, 16384 * 8);
#endif

    unsigned int *data = (unsigned int *)(DDR_MEM_BASEADDR + 0x800000);

    for(int i = 0; i < 16384 * 8; i++)
            printf("\n 0x%03x", *(data + i));

	printf("Done\n");

	return 0;

Sergiu

Hi Sergiu, thank your for the answer

I tried it today,  but the code is stuck in   "axi_dmac_tranfer function" at the below code lines which probably means that current transfer cannot be completed.   reg_val  is always 1  in this piece of code.  What can be the reasons ?  

do {
		axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
	} while(reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT));

Hi HasanSatana,

HasanSatana said:

All no-os system is working correctly in Xilinx SDK with no-os drivers provided in the master-branch. 

HasanSatana said:

I tried it today,  but the code is stuck in   "axi_dmac_tranfer function" at the below code

In the original post you said the project works with master branch.

Then you said the transfer is stuck.

What code and hdl version you use when you say the transfer function is stuck ? It clearly cannot be the same

Hi, thank you, 

it was my mistake that I put a debug port wrongly in the hdl design. It is OK now after a clear implementation.

I am trying to observe change in the 'fifo_wr_sync'  port of the 'axi_rx_dma IP' with the  "axi_dmac_transfer"   during receiving. I thought it will be 1 after sending "axi_dmac_transfer" function, however, it becomes 1 after axi_adc_init() function and stays 1 always afterwards.

What is happening after sending the "axi_dmac_transfer" function ? Is it related to interrupts ?  

Hi, thank you, 

it was my mistake that I put a debug port wrongly in the hdl design. It is OK now after a clear implementation.

I am trying to observe change in the 'fifo_wr_sync'  port of the 'axi_rx_dma IP' with the  "axi_dmac_transfer"   during receiving. I thought it will be 1 after sending "axi_dmac_transfer" function, however, it becomes 1 after axi_adc_init() function and stays 1 always afterwards.

What is happening after sending the "axi_dmac_transfer" function ? Is it related to interrupts ?  

HI Hasan,

Here is a wiki page for the DMA: https://wiki.analog.com/resources/fpga/docs/axi_dmac

Sergiu

HasanSatana,

I'm marking your answer as verified answer since you said it was a mistake in your custom hdl.

For you other question, please check the doc and, if still unclear, post a new thread with that question.

Let's not have multiple questions per thread.