HMC7043 no os driver cannot create precise clock

Hi there,

I am using HMC7043 to create clock 245.76Mhz on channel 2-4-6-8-10  and 960kHz as reference clock on channel 11. However, when I use driver of 7043 supported by ADI, channel 4-6-8-10 ouputs with clock of 960kHz while channel 2 output has weird behavior of clock 148Mhz. 

Here is my configuration for 7043:

struct hmc7044_init_param hmc7043_param = {
.spi_init = NULL,
.is_hmc7043 = true,
.clkin_freq = {122880000, 0, 0, 0},
//.vcxo_freq = 122880000,
//.pll2_freq = 2457600000,
//.pll1_loop_bw = 200,
.sysref_timer_div = 1280,
.in_buf_mode = {0x07, 0x07, 0x00, 0x00, 0x00},
.gpi_ctrl = {0x00, 0x00, 0x00, 0x00},
.gpo_ctrl = {0x0f, 0x09, 0x35, 0x01},
.num_channels = 14, //<-- number of channels in .channels.
.pll1_ref_prio_ctrl = 0xB1,
.sync_pin_mode = 0x1,
.high_performance_mode_clock_dist_en = true,
.high_performance_mode_pll_vco_en = true,
.pulse_gen_mode = 0x07,
.channels = chan_spec
};

struct hmc7044_chan_spec 7043_chan_spec[14] = {
/* FPGA0_CLK */
{
.disable = 0, .num = 2, .divider = 5, .driver_mode = 2,
.start_up_mode_dynamic_enable = false
},
/* FMC_CLK */
{
.disable = 0, .num = 4, .divider = 5, .driver_mode = 2,
.start_up_mode_dynamic_enable = false
},
/* FPGA2_CLK */
{
.disable = 0, .num = 6, .divider = 5, .driver_mode = 2,
.start_up_mode_dynamic_enable = false
},
/* FPGA3_CLK */
{
.disable = 0, .num = 8, .divider = 5, .driver_mode = 2,
.start_up_mode_dynamic_enable = false
},
/* FPGA4_CLK */
{
.disable = 0, .num = 10, .divider = 5, .driver_mode = 2,
.start_up_mode_dynamic_enable = false
},
/* FMC_SYSREF */
{
.disable = 0, .num = 11, .divider = 1280, .driver_mode = 2,
.start_up_mode_dynamic_enable = false
}
};

Top Replies

  • Hi there, 

    I am trying to deploy a system of HMC7044 and HMC7043 generating clock  for Jesd204B like the following figure using no-os driver. Although I can configure RX and R_OS of Jesd204B, TX status register gets error. How can I check that my clock generating system works well without using oscilloscope and any approach to solve my TX configuration problem? I am not using GPIO to reset HMC7044 and 7043. Configuration struct like this:

    struct hmc7044_init_param hmc7044_param = {
         .spi_init = NULL,
        .clkin_freq = {0, 0, 0, 122880000},
        .vcxo_freq = 122880000,
        .pll2_freq = 2457600000,
        .pll1_loop_bw = 200,
        .sysref_timer_div = 2560,
        .in_buf_mode = {0x00, 0x00, 0x00, 0x07, 0x03},
        .gpi_ctrl = {0x00, 0x00, 0x00, 0x11},
       .gpo_ctrl = {0x3f, 0x0E, 0x0A, 0x09},
       .num_channels = 14, //<-- number of channels in .channels.
       .pll1_ref_prio_ctrl = 0xB1,
       .sync_pin_mode = 0x1,
       .high_performance_mode_clock_dist_en = true,
       .high_performance_mode_pll_vco_en = true,
       .pulse_gen_mode = 0x07,
       .channels = chan_spec
    };

    struct hmc7044_init_param hmc7043_param = {
       .spi_init = NULL,
       .is_hmc7043 = true,
       .clkin_freq = {122880000, 0, 0, 0},
       //.vcxo_freq = 122880000,
       //.pll2_freq = 2457600000,
       //.pll1_loop_bw = 200,
       .sysref_timer_div = 1280,
       .in_buf_mode = {0x07, 0x07, 0x00, 0x00, 0x00},
       .gpi_ctrl = {0x00, 0x00, 0x00, 0x00},
       .gpo_ctrl = {0x0f, 0x09, 0x35, 0x01},
       .num_channels = 14, //<-- number of channels in .channels.
       .pll1_ref_prio_ctrl = 0xB1,
       .sync_pin_mode = 0x1,
       .high_performance_mode_clock_dist_en = true,
       .high_performance_mode_pll_vco_en = true,
       .pulse_gen_mode = 0x07,
       .channels = chan_spec
    };

    a channel spec is:

    struct hmc7044_chan_spec 7044_chan_spec[14] = {
    /* HMC7043_CLK */
    {
    .disable = 0, .num = 0, .divider = 12, .driver_mode = 2,
    .start_up_mode_dynamic_enable = false
    },
    /* HMC7043_SYSREF */
    {
    .disable = 0, .num = 1, .divider = 2560, .driver_mode = 2,
    .start_up_mode_dynamic_enable = true
    },

  • 0
    •  Analog Employees 
    on Dec 8, 2020 7:37 AM in reply to LeoTungAnh

    Hi,

    You can implemented something similar to the Linux hmc7044_status_show()https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/frequency/hmc7044.c#L1488

    We'll do that too on our no-OS master branch soon. We'll let you know when it's available.

    Thanks,
    Dragos

  • I used oscilloscope to measure clock on 7044. It can generate clock for 7043, however, created clocks on all channels of 7043 are the same with 96KHz. 

  • It's not the thing which I am looking for. I used driver to create clock of 24,546Mhz like this

    ret = hmc7044_clk_set_rate(7043_clkchip_device, FPGA2_CLK,24576000);

  • 0
    •  Analog Employees 
    on Dec 11, 2020 3:21 PM

    Hi,

    Can you give us more details about your hardware?

    Thanks,
    Dragos

  • Hi Dragos,

    I want to create clock 245.76Mhz on channel 2-4-6-8-10 of HMC7043 and 960kHz on channel 11 of 7043 is SYSREF clock. 

    The input clock of 7043 is received from HMC7044 with 1228800000 (~1.2Ghz) and SYSREF for 7043 is 960kHz.

    The problem is that on channels 4-6-8-10 output is the same with 960kHz and channel 2 outputs a weird clock.

    I am using the driver of ADI on linux and it work, but driver for no-os does not work as expected

    Bests,

    Tung Anh

  • 0
    •  Analog Employees 
    on Dec 14, 2020 7:17 AM in reply to LeoTungAnh

    ,

    I think DragosB question is more like, are you running custom board ? Or the standard projects used in our official projects ? Please specify the hardware (e.g.: zcu102 + adrv9009w/pcbz)

  • I use a custom board where I use ZU15EG isntead of ZU9EG on ZCU102. However, when using linux everything is okay, problems only occur when I use driver on no os  for 7043 which does not have precede example.

  • 0
    •  Analog Employees 
    on Dec 14, 2020 8:56 AM in reply to LeoTungAnh

    ,

    Could you please post the linux device tree configuration for hmc7043 that you say works for you for comparison ?

  • /include/ "system-conf.dtsi"
    #include <dt-bindings/leds/leds-pca955x.h>
    / {
    model = "ZynqMP ZCU102 Rev1.0";
    compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";

    /*
    chosen {
    bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused uio_pdrv_genirq.of_id=generic-uio";
    stdout-path = "serial0:115200n8";
    };
    */


    chosen {
    bootargs = "earlycon clk_ignore_unused cpuidle.off=1 uio_pdrv_genirq.of_id=generic-uio mem=2G root=/dev/mtdblock3 rw rootfstype=jffs2";
    };

    aliases {
    ethernet0 = &gem3;
    i2c0 = &i2c0;
    i2c1 = &i2c1;
    serial0 = &uart0;
    serial1 = &uart1;
    spi0 = &qspi;
    spi1 = &spi0;
    spi2 = &spi1;

    // HMC7044 & HMC7043
    spi4 = &spi4;
    spi5 = &spi5;

    // ADRV9009
    spi6 = &spi6;
    spi7 = &spi7;
    spi8 = &spi8;
    spi9 = &spi9;
    spi10 = &spi10;
    };

    fakeiio: fakeiio {
    compatible = "viettel,fakeiio";
    status = "okay";
    };

    rrugpio: rrugpio {
    compatible = "viettel,rrugpio";
    status = "okay";
    };

    ipcore: ipcore {
    compatible = "viettel,ipcore";
    status = "okay";
    };

    spi4: spi4 {
    compatible = "spi-gpio";
    #address-cells = <0x1>;
    status = "okay";
    gpio-sck = <&gpio 106 0>; // EMIO 28
    gpio-miso = <&gpio 93 0>; // EMIO 15
    gpio-mosi = <&gpio 94 0>; // EMIO 16

    cs-gpios = <&gpio 107 0>; // EMIO 29
    num-chipselects = <1>;
    bits-per-word = <8>;

    clk0_hmc7044: hmc7044-1@0 {
    compatible = "adi,hmc7044";
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    spi-max-frequency = <10000000>;
    #clock-cells = <1>;

    switch-gpios = <&gpio 95 0>;// EMIO 17

    reset-gpios = <&gpio 132 0>;// EMIO 54

    adi,pll1-clkin-frequencies = <0 0 0 122880000>;

    adi,pll1-loop-bandwidth = <200>;

    adi,vcxo-frequency = <122880000>;

    adi,pll2-output-frequency = <2457600000>;

    adi,sysref-timer-divider = <2560>;
    adi,pulse-generator-mode = <7>;

    adi,clkin3-buffer-mode = <0x07>;
    adi,oscin-buffer-mode = <0x03>;

    adi,gpi-controls = <0x00 0x00 0x00 0x11>;
    adi,gpo-controls = <0x3f 0x0E 0x0A 0x09>;

    clock-output-names = "hmc7044-1_out0", "hmc7044-1_out1", "hmc7044-1_out2",
    "hmc7044-1_out3", "hmc7044-1_out4", "hmc7044-1_out5",
    "hmc7044-1_out6", "hmc7044-1_out7", "hmc7044-1_out8",
    "hmc7044-1_out9", "hmc7044-1_out10", "hmc7044-1_out11",
    "hmc7044-1_out12", "hmc7044-1_out13";


    hmc7044_0_c0: channel@0 {
    reg = <0>;
    adi,extended-name = "HMC7043_CLK";
    adi,divider = <2>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c1: channel@1 {
    reg = <1>;
    adi,extended-name = "HMC7043_SYSREF";
    adi,divider = <2560>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <1>;
    };
    hmc7044_0_c2: channel@2 {
    reg = <2>;
    adi,extended-name = "ADRV0_CLK";
    adi,divider = <10>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c3: channel@3 {
    reg = <3>;
    adi,extended-name = "ADRV0_SYSREF";
    adi,divider = <2560>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c4: channel@4 {
    reg = <4>;
    adi,extended-name = "ADRV2_CLK";
    adi,divider = <10>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c5: channel@5 {
    reg = <5>;
    adi,extended-name = "ADRV2_SYSREF";
    adi,divider = <2560>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c6: channel@6 {
    reg = <6>;
    adi,extended-name = "DEV_CLK";
    adi,divider = <10>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c7: channel@7 {
    reg = <7>;
    adi,extended-name = "DEV_SYSREF";
    adi,divider = <2560>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c8: channel@8 {
    reg = <8>;
    adi,extended-name = "ADRV4_CLK";
    adi,divider = <10>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c9: channel@9 {
    reg = <9>;
    adi,extended-name = "ADRV4_SYSREF";
    adi,divider = <2560>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c10: channel@10 {
    reg = <10>;
    adi,extended-name = "ADRV3_CLK";
    adi,divider = <10>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c11: channel@11 {
    reg = <11>;
    adi,extended-name = "ADRV3_SYSREF";
    adi,divider = <2560>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c12: channel@12 {
    reg = <12>;
    adi,extended-name = "EX_CLK";
    adi,divider = <2>;
    adi,driver-mode = <0>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7044_0_c13: channel@13 {
    reg = <13>;
    adi,extended-name = "EX_SYSREF";
    adi,divider = <2560>;
    adi,driver-mode = <0>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    };

    };

    spi5: spi5 {
    compatible = "spi-gpio";
    #address-cells = <0x1>;
    status = "okay";
    gpio-sck = <&gpio 109 0>; // EMIO 31
    gpio-miso = <&gpio 90 0>; // EMIO 12
    gpio-mosi = <&gpio 91 0>; // EMIO 13

    cs-gpios = <&gpio 110 0>; // EMIO 32
    num-chipselects = <1>;
    bits-per-word = <8>;

    clk0_hmc7043: hmc7043-1@0 {
    compatible = "adi,hmc7043";
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    #clock-cells = <1>;

    spi-max-frequency = <10000000>;

    switch-gpios = <&gpio 92 0>;// EMIO 14

    reset-gpios = <&gpio 133 0>;// EMIO 55

    adi,input-frequency = <1228800000>;

    adi,sysref-timer-divider = <1280>;
    adi,pulse-generator-mode = <7>;

    adi,clkin0-buffer-mode = <0x07>;
    adi,clkin1-buffer-mode = <0x07>;

    adi,gpi-controls = <0x00 0x00 0x00 0x00>;
    adi,gpo-controls = <0x0F 0x09 0x35 0x01>;

    clock-output-names = "hmc7043-1_out0", "hmc7043-1_out1", "hmc7043-1_out2",
    "hmc7043-1_out3", "hmc7043-1_out4", "hmc7043-1_out5",
    "hmc7043-1_out6", "hmc7043-1_out7", "hmc7043-1_out8",
    "hmc7043-1_out9", "hmc7043-1_out10", "hmc7043-1_out11",
    "hmc7043-1_out12", "hmc7043-1_out13";


    hmc7043_0_c2: channel@2 {
    reg = <2>;
    adi,extended-name = "FPGA0_CLK";
    adi,divider = <5>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7043_0_c4: channel@4 {
    reg = <4>;
    adi,extended-name = "FMC_CLK";
    adi,divider = <5>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7043_0_c6: channel@6 {
    reg = <6>;
    adi,extended-name = "FPGA2_CLK";
    adi,divider = <5>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7043_0_c8: channel@8 {
    reg = <8>;
    adi,extended-name = "FPGA3_CLK";
    adi,divider = <5>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7043_0_c10: channel@10 {
    reg = <10>;
    adi,extended-name = "FPGA4_CLK";
    adi,divider = <5>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    hmc7043_0_c11: channel@11 {
    reg = <11>;
    adi,extended-name = "FMC_SYSREF";
    adi,divider = <1280>;
    adi,driver-mode = <2>;
    adi,startup-mode-dynamic-enable = <0>;
    };
    };


    };

    fpga_axi: fpga-axi@0 {
    interrupt-parent = <&gic>;
    compatible = "simple-bus";
    #address-cells = <0x1>;
    #size-cells = <0x1>;
    ranges = <0 0 0 0xffffffff>;

    fake_fpga_clk: fake_fpga_clk {
    #clock-cells = <0x0>;
    clock-frequency = <245760000>;
    compatible = "fixed-clock";
    };

    axi_adrv9009_core_rx: axi-adrv9009-rx-hpc@84a00000 {
    compatible = "adi,axi-adrv9009-rx-1.0";
    reg = <0x84a00000 0x8000>;
    //dmas = <&rx_dma 0>;
    //dma-names = "rx";
    spibus-connected = <&trx12_adrv9009>;
    };

    axi_adrv9009_core_rx_obs: axi-adrv9009-rx-obs-hpc@84a08000 {
    compatible = "adi,axi-adrv9009-obs-1.0";
    reg = <0x84a08000 0x1000>;
    //dmas = <&rx_obs_dma 0>;
    //dma-names = "rx";
    clocks = <&trx12_adrv9009 1>;
    clock-names = "sampl_clk";
    };

    axi_adrv9009_core_tx: axi-adrv9009-tx-hpc@84a04000 {
    compatible = "adi,axi-adrv9009-tx-1.0";
    reg = <0x84a04000 0x4000>;
    //dmas = <&tx_dma 0>;
    //dma-names = "tx";
    clocks = <&trx12_adrv9009 2>;
    clock-names = "sampl_clk";
    spibus-connected = <&trx12_adrv9009>;
    //adi,axi-pl-fifo-enable;
    };

    axi_adrv9009_rx_jesd: axi-jesd204-rx@84aa0000 {
    compatible = "adi,axi-jesd204-rx-1.0";
    reg = <0x84aa0000 0x1000>;

    interrupts = <0 106 0>;

    clocks = <&clk 71>, <&axi_rx_clkgen>, <&axi_adrv9009_adxcvr_rx 0>;
    clock-names = "s_axi_aclk", "device_clk", "lane_clk";

    #clock-cells = <0>;
    clock-output-names = "jesd_rx_lane_clk";

    adi,octets-per-frame = <4>;
    adi,frames-per-multiframe = <32>;
    };

    axi_adrv9009_tx_jesd: axi-jesd204-tx@84a90000 {
    compatible = "adi,axi-jesd204-tx-1.0";
    reg = <0x84a90000 0x1000>;

    interrupts = <0 105 0>;

    clocks = <&clk 71>, <&axi_tx_clkgen>, <&axi_adrv9009_adxcvr_tx 0>;
    clock-names = "s_axi_aclk", "device_clk", "lane_clk";

    #clock-cells = <0>;
    clock-output-names = "jesd_tx_lane_clk";

    adi,octets-per-frame = <2>;
    adi,frames-per-multiframe = <32>;
    adi,converter-resolution = <14>;
    adi,bits-per-sample = <16>;
    adi,converters-per-device = <4>;
    adi,control-bits-per-sample = <2>;
    };

    axi_adrv9009_rx_os_jesd: axi-jesd204-rx-os@84ab0000 {
    compatible = "adi,axi-jesd204-rx-1.0";
    reg = <0x84ab0000 0x1000>;

    interrupts = <0 104 0>;

    clocks = <&clk 71>, <&axi_rx_os_clkgen>, <&axi_adrv9009_adxcvr_rx_os 0>;
    clock-names = "s_axi_aclk", "device_clk", "lane_clk";

    #clock-cells = <0>;
    clock-output-names = "jesd_rx_os_lane_clk";

    adi,octets-per-frame = <4>;
    adi,frames-per-multiframe = <32>;
    };

    axi_tx_clkgen: axi-clkgen@83c00000 {
    compatible = "adi,axi-clkgen-2.00.a";
    reg = <0x83c00000 0x10000>;
    #clock-cells = <0>;
    clocks = <&clk0_hmc7043 4>;
    clock-output-names = "axi_tx_clkgen";
    };

    axi_rx_clkgen: axi-clkgen@83c10000 {
    compatible = "adi,axi-clkgen-2.00.a";
    reg = <0x83c10000 0x10000>;
    #clock-cells = <0>;
    clocks = <&clk0_hmc7043 4>;
    clock-output-names = "axi_rx_clkgen";
    };

    axi_rx_os_clkgen: axi-clkgen@83c20000 {
    compatible = "adi,axi-clkgen-2.00.a";
    reg = <0x83c20000 0x10000>;
    #clock-cells = <0>;
    clocks = <&clk0_hmc7043 4>;
    clock-output-names = "axi_rx_os_clkgen";
    };

    axi_adrv9009_adxcvr_rx: axi-adxcvr-rx@84a60000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "adi,axi-adxcvr-1.0";
    reg = <0x84a60000 0x1000>;

    clocks = <&clk0_hmc7043 4>, <&axi_rx_clkgen 0>;
    clock-names = "conv", "div40";

    #clock-cells = <1>;
    clock-output-names = "rx_gt_clk", "rx_out_clk";

    adi,sys-clk-select = <0>;
    adi,out-clk-select = <3>;
    adi,use-lpm-enable;
    adi,use-cpll-enable;
    };

    axi_adrv9009_adxcvr_rx_os: axi-adxcvr-rx-os@84a50000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "adi,axi-adxcvr-1.0";
    reg = <0x84a50000 0x1000>;

    clocks = <&clk0_hmc7043 4>, <&axi_rx_os_clkgen>;
    clock-names = "conv", "div40";

    #clock-cells = <1>;
    clock-output-names = "rx_os_gt_clk", "rx_os_out_clk";

    adi,sys-clk-select = <0>;
    adi,out-clk-select = <3>;
    adi,use-lpm-enable;
    adi,use-cpll-enable;
    };

    axi_adrv9009_adxcvr_tx: axi-adxcvr-tx@84a80000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "adi,axi-adxcvr-1.0";
    reg = <0x84a80000 0x1000>;

    clocks = <&clk0_hmc7043 4>, <&axi_tx_clkgen>;
    clock-names = "conv", "div40";

    #clock-cells = <1>;
    clock-output-names = "tx_gt_clk", "tx_out_clk";

    adi,sys-clk-select = <3>;
    adi,out-clk-select = <3>;
    };

    };

    spi6: spi6 {
    compatible = "spi-gpio";
    #address-cells = <0x1>;
    status = "okay";
    gpio-sck = <&gpio 113 0>; // EMIO 35
    gpio-miso = <&gpio 147 0>; // EMIO 69
    gpio-mosi = <&gpio 112 0>; // EMIO 34
    cs-gpios = <&gpio 111 0>; // EMIO 33
    num-chipselects = <1>;
    bits-per-word = <8>;
    };

    spi7: spi7 {
    compatible = "spi-gpio";
    #address-cells = <0x1>;
    status = "okay";
    gpio-sck = <&gpio 116 0>; // EMIO 38
    gpio-miso = <&gpio 149 0>; // EMIO 71
    gpio-mosi = <&gpio 115 0>; // EMIO 37
    cs-gpios = <&gpio 114 0>; // EMIO 36
    num-chipselects = <1>;
    bits-per-word = <8>;
    };

    spi8: spi8 {
    compatible = "spi-gpio";
    #address-cells = <0x1>;
    status = "okay";
    gpio-sck = <&gpio 119 0>; // EMIO 41
    gpio-miso = <&gpio 151 0>; // EMIO 73
    gpio-mosi = <&gpio 118 0>; // EMIO 40
    cs-gpios = <&gpio 117 0>; // EMIO 39
    num-chipselects = <1>;
    bits-per-word = <8>;
    };

    spi9: spi9 {
    compatible = "spi-gpio";
    #address-cells = <0x1>;
    status = "okay";
    gpio-sck = <&gpio 122 0>; // EMIO 44
    gpio-miso = <&gpio 153 0>; // EMIO 75
    gpio-mosi = <&gpio 121 0>; // EMIO 43
    cs-gpios = <&gpio 120 0>; // EMIO 42
    num-chipselects = <1>;
    bits-per-word = <8>;
    };

    spi10: spi10 {
    compatible = "spi-gpio";
    #address-cells = <0x1>;
    status = "okay";
    gpio-sck = <&gpio 125 0>; // EMIO 47
    gpio-miso = <&gpio 155 0>; // EMIO 77
    gpio-mosi = <&gpio 124 0>; // EMIO 46
    cs-gpios = <&gpio 123 0>; // EMIO 45
    num-chipselects = <1>;
    bits-per-word = <8>;
    };

    };

    #define adrv9009_rfe_1 spi6
    #define adrv9009_rfe_2 spi7
    #define adrv9009_rfe_3 spi8
    #define adrv9009_rfe_4 spi9
    #define adrv9009_calib spi10

    &spi0 {
    status = "okay";
    };

    &i2c0 {
    clock-frequency = <100000>;
    /delete-node/ gpio@20;
    /delete-node/ gpio@21;
    /delete-node/ i2c-mux@75;
    // Must add CPLD I2C mux here
    cpld_mux@78 {
    compatible = "viettel,cpld_i2c-mux";
    reg = <0x78>;
    #address-cells = <1>;
    #size-cells = <0>;

    i2c@1 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x01>;

    sfp_1_vendor: sfp_1_vendor@50 {
    compatible = "viettel,sfp_1_vendor";
    reg = <0x50>;
    };
    sfp_1_diagnostic: sfp_1_diagnostic@51 {
    compatible = "viettel,sfp_1_diagnostic";
    reg = <0x51>;
    };
    };

    i2c@2 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x02>;

    sfp_2_vendor: sfp_2_vendor@50 {
    compatible = "viettel,sfp_2_vendor";
    reg = <0x50>;
    };
    sfp_2_diagnostic: sfp_2_diagnostic@51 {
    compatible = "viettel,sfp_2_diagnostic";
    reg = <0x51>;
    };
    };

    i2c@3 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x03>;

    sfp_3_vendor: sfp_3_vendor@50 {
    compatible = "viettel,sfp_3_vendor";
    reg = <0x50>;
    };
    sfp_3_diagnostic: sfp_3_diagnostic@51 {
    compatible = "viettel,sfp_3_diagnostic";
    reg = <0x51>;
    };
    };

    i2c@4 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x04>;

    sfp_4_vendor: sfp_4_vendor@50 {
    compatible = "viettel,sfp_4_vendor";
    reg = <0x50>;
    };
    sfp_4_diagnostic: sfp_4_diagnostic@51 {
    compatible = "viettel,sfp_4_diagnostic";
    reg = <0x51>;
    };
    };

    i2c@5 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x05>;

    lmk05028@60 {
    compatible = "ti,lmk05028";
    reg = <0x60>;
    reset-gpios = <&gpio 131 0>;
    };
    };

    i2c@6 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x06>;
    };

    i2c@7 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x07>;

    eeprom: eeprom@54 {
    compatible = "at,24c08";
    reg = <0x54>;
    };
    };

    i2c@8 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x08>;

    adt7420: adt7420@48 {
    compatible = "adi,adt7420";
    reg = <0x48>;
    };
    };

    i2c@9 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x09>;

    ina226_1: ina226_12v@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <3000>;
    };
    };

    i2c@a {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x0a>;

    ina226_2: ina226_28v@40 {
    compatible = "ti,ina226";
    reg = <0x41>;
    shunt-resistor = <2000>;
    };

    pca9551: pca9551@60 {
    compatible = "nxp,pca9551";
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x60>;

    cpri0@0 {
    label = "cpri0";
    reg = <0>;
    type = <PCA955X_TYPE_LED>;
    linux,default-trigger = "default-on";
    };
    cpri1@1 {
    label = "cpri1";
    reg = <1>;
    type = <PCA955X_TYPE_LED>;
    linux,default-trigger = "default-on";
    };
    cpri2@2 {
    label = "cpri2";
    reg = <2>;
    type = <PCA955X_TYPE_LED>;
    linux,default-trigger = "default-on";
    };
    cpri3@3 {
    label = "cpri3";
    reg = <3>;
    type = <PCA955X_TYPE_LED>;
    linux,default-trigger = "default-on";
    };
    alarm@7 {
    label = "alarm";
    reg = <7>;
    type = <PCA955X_TYPE_LED>;
    linux,default-trigger = "default-on";
    };
    };

    lm73: lm73@0 {
    compatible = "ti,lm73";
    reg = <0x4A>;
    };
    };

    i2c@b {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x0b>;

    ina226_3: ina226_3v3_vcco@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@c {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x0c>;

    ina226_4: ina226_1v8_vccaux@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@d {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x0d>;

    ina226_5: ina226_1v8_vcco@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@e {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x0e>;

    ina226_6: ina226_1v2_vmgtavtt@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@f {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x0f>;

    ina226_7: ina226_1v2_vcco@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@10 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x10>;

    ina226_8: ina226_0v9_vmgtavcc@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@11 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x11>;

    ina226_9: ina226_0v85_vccpsintlp@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@12 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x12>;

    ina226_10: ina226_0v85_vccint@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@13 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x13>;

    ina226_11: ina226_0v85_vccpsintfp@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };

    i2c@14 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0x14>;

    ina226_12: ina226_28v_pa@40 {
    compatible = "ti,ina226";
    reg = <0x40>;
    shunt-resistor = <2000>;
    };
    };
    };
    };

    &i2c1 {
    /delete-node/ i2c-mux@74;
    /delete-node/ i2c-mux@74;
    /delete-node/ i2c-mux@75;
    };

    &qspi {
    is-dual = <0>;
    flash0: flash@0 {
    compatible = "mt25ql02g","micron,m25p80";
    };
    };

    &gem3 {
    /delete-property/ phy-handle;
    /delete-node/ phy@c;
    };

    &nand0 {
    status = "okay";
    arasan,has-mdma;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_nand0_default>; // must add pinctrl for NAND
    nand@0 {
    reg = <0x0>;
    #address-cells = <0x2>;
    #size-cells = <0x1>;
    partition@0 {
    label = "nand-fsbl-uboot";
    reg = <0x0 0x0 0x400000>;
    };
    partition@1 {
    label = "nand-linux";
    reg = <0x0 0x400000 0x1400000>;
    };
    partition@2 {
    label = "nand-device-tree";
    reg = <0x0 0x1800000 0x400000>;
    };
    partition@3 {
    label = "nand-rootfs";
    reg = <0x0 0x1C00000 0x1400000>;
    };
    partition@4 {
    label = "nand-bitstream";
    reg = <0x0 0x3000000 0x400000>;
    };
    partition@5 {
    label = "nand-misc";
    reg = <0x0 0x3400000 0xFCC00000>;
    };
    };
    };

    &amba_pl{

    /delete-node/ axi_clkgen@83c10000;
    /delete-node/ axi_clkgen@83c00000;
    /delete-node/ axi_clkgen@83c20000;

    /delete-node/ axi_ad9371@84a00000;

    /delete-node/ axi_jesd204_rx@84aa0000;
    /delete-node/ axi_jesd204_rx@84ab0000;
    /delete-node/ axi_jesd204_tx@84a90000;

    /delete-node/ axi_adxcvr@84a80000;
    /delete-node/ axi_adxcvr@84a60000;
    /delete-node/ axi_adxcvr@84a50000;

    /delete-node/ dpd@80080000;

    /delete-node/ gpio@91000000;
    /delete-node/ gpio@91001000;
    /delete-node/ gpio@91002000;
    /delete-node/ gpio@91003000;
    /delete-node/ gpio@91004000;

    DFE_dpd_0: dpd@80080000 {
    clock-names = "dpd_aclk", "dpd_internal_aclk", "s_axi_ctrl_aclk", "s_axi_user_aclk";
    clocks = <&misc_clk_0>, <&misc_clk_0>, <&clk 71>, <&clk 71>;
    compatible = "xlnx,dpd-9.0";
    interrupt-names = "interrupt";
    interrupt-parent = <&gic>;
    interrupts = <0 109 1>;
    reg = <0x0 0x88000000 0x0 0x4000000 0x0 0x80080000 0x0 0x20000>;
    };

    };

    &DFE_dpd_0{
    compatible = "generic-uio";
    };

    / {

    };

    #include "pinctrl-8T8R.dtsi"
    #include "adi-adrv9009-dfe1-8T8R-hmc7044-clk.dtsi"
    //#include "adi-adrv9009-dfe2-8T8R-hmc7044-clk.dtsi"
    //#include "adi-adrv9009-dfe3-8T8R-hmc7044-clk.dtsi"
    //#include "adi-adrv9009-dfe4-8T8R-hmc7044-clk.dtsi"
    //#include "adi-adrv9009-calib-8T8R-hmc7044-clk.dtsi"