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AD-FREQCVT1 - SPI pins wiring

Nickbiz
on Nov 20, 2020

Hello,

I am using a microcontroller to program ADF4351's 6 registers on this board using SPI via P2 header pins. See layout of the P2 header pins below:

Here is my wirings:

- Pins P2-1 and P2-2 are the LE pin (active low)

- Pins P2-3 and P2-7 are data and clock pins

- Pins P2-9 and P2-10 are connected to GND pin of the microcontroller.

- Pins P2-11 and P2-12 are connected to 3v3 source of the microcontroller. (not sure what this pin is for)

Is it correct ?

What do pins P2-11 and P2-12 do ?

I am asking so because I have trouble reading back MUX_OUT pins using a multimeter.

Most of the time, it didn't work. I was rarely able to read back some changes on the MUX_OUT pins.

I tried to set LD pins through register 5 on the ADF4351 to high, to turn on LED DS1 and DS2. But It was successful only a couple of times.

I am not sure what's the problem. Any suggestion ?

https://wiki.analog.com/resources/eval/user-guides/ad-freqcvt1-ebz/hardware/functional_overview#lo

Thanks

Nick

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  • +1
    •  Analog Employees 
    on Nov 21, 2020 8:39 AM 3 months ago in reply to Nickbiz

    The only other thing that comes to mind, from a hardware point of view, is the signal integrity on the SPI bus. What is the frequency of the SPI signals?

    Can you use an oscilloscope to analyze the SPI signals?

    Also, check pins P2-1 and P2-2. LE is not specified as active low in the datasheet of ADF4351.

    Regards,

    Andreea 

  • 0 on Nov 22, 2020 7:01 PM 3 months ago in reply to andreeapop

    The SPI clock is below 1 Mhz. Is there a specific frequency range that ADF4351 expecting ?

    I don't have an oscilloscope. But I have a cheap logic analyzer. I'm not sure how reliable it is, but when I checked the SPI signals, the clk was not stable. I saw the clk period changing slightly at several places, causing the logic analyzer to read in incorrect values at the SIMO wire. It may be the problem here. I'll use another microcontroller to test it again.

    About the LE signal, according to ADF4351 datasheet, page 5 and 26, the LE should go low during register write and go high let the ADF4351 know the write is completed. The new value for each register is latched at LE=1.

    Thanks

    Nick