Actually, I'm trying to make work the provided talise application without modifying the hw project.
I want to test the axi_dac_load_custom_data of the provided sine_lut_iq table. My LO is at 1GHz and I have used the "tx_bw100_ir122p88_rx_bw100_or122p88_orx_bw100_or122p88_dc122p88" profile. When I tried to see the output signal on the spectrum analyzer, I can see the 1.002 GHz frequency(LO + base signal) but I also have a 100MHz of Bw around the LO frequency which is undesirable for my future application (ScreenShot1)
I have tried to send DDS frequency using "axi_dac_dds_set_frequency" and it works percfectly. I have got a pic at LO+dds frequency and 100mV peak-2peak of amplitude since I have scaled the signal with 100mUnits (axi_dac_dds_set_scale(dac, ((ch*2)+1), 100*1000)) (ScreenShot2)
When I put the scale on more than 500mUnits axi_dac_dds_set_scale(dac, ((ch*2)+1), 500*1000), some harmonics are shown on my spectrum analyzer (ScreenShot3)
I tried so to decrease the amplitude of the sine_lut_iq signal and code it on 16 bits and then on 12 bits but unfortunately I have got the same signal amplitude = 60mV and some harmonics around the LO frequency. What is the relation in number between the number of bits used for the sine_lut_iq and the signal amplitude. I could'nt confirm that the signal amplitude saturates the amplifier and so causes the harmonics. Could you please explain me these phenomenas.
The AXI_DAC_DDS is actually a dual tone generator - it generates two tones as two signals for each TX channel. These two signals are summed up and send as one signal to the DAC channel. So, make sure…
The AXI_DAC_DDS is actually a dual tone generator - it generates two tones as two signals for each TX channel. These two signals are summed up and send as one signal to the DAC channel. So, make sure the sum of the scales doesn't exceed 1.
Regarding to the TX DMA, do you have the TX FIFO enabled?
I have loaded the last configuration files (talise_config.c) and it works good. thank you.