IIO with Arria 10 GX + ADRV9371-W

I am trying to connect to my ADRV9371-W using libiio 0.21 on Centos 7. I have my ADRV9371-W connected to the FMC of my Arria 10 GX, which is connected via the USB and in the PCIe port of the Centos box, and I have compiled the HDL and no-OS repos and successfully run the reference no-OS application (headless.c). I installed libiio with USB support and recompiled the no-OS application with TINYIIOD=y to enable iio support, but I can not find the ADRV9371-W + Arria 10 GX in my device list when I run iio_info -s or iio_attr -a -d. They show no devices and only the local context.

Any assistance in tracking down why my libiio setup cannot find the USB would be greatly appreciated.

  • 0
    •  Analog Employees 
    on Oct 22, 2020 6:37 PM 1 month ago

    libiio cannot auto-scan for serial devices. You need to specify the URI explicitly like: serial:/dev/ttyUSB0,115200,8n1

    -Travis

  • I have the same issue. I used "serial:/dev/ttyUSB0,115200,8n1" in IIO Oscilloscope but still can't connect. Note: I can see there is a /dev/ttyUSB0 device.

    I tried this command in terminal, but still got no context

    $ iio_writedev -u serial:/dev/ttyUSB0,921600 -b 400 system_bd.sopcinfo 
    Unable to create IIO context serial:/dev/ttyUSB0,921600: Function not implemented

    I followed this guide https://wiki.analog.com/resources/tools-software/no-os-software/iio

    Here is output messages after I program the board with sof (HDL branch "qpro_master", and No-OS branch is "2019_R1", Quartus Pro 19.2)

    $ nios2-configure-sof 
    Searching for SOF file:
    in .
      adrv9371x_a10gx_time_limited.sof
    
    Warning (210039): File ./adrv9371x_a10gx_time_limited.sof contains one or more time-limited megafunctions that support the Intel FPGA IP Evaluation Mode feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.
    Info (210040): SRAM Object File ./adrv9371x_a10gx_time_limited.sof contains time-limited megafunction that supports Intel FPGA IP Evaluation Mode feature -- Vendor: 0x6AF7, Product: 0x00A2
    Info (210040): SRAM Object File ./adrv9371x_a10gx_time_limited.sof contains time-limited megafunction that supports Intel FPGA IP Evaluation Mode feature -- Vendor: 0x6AF7, Product: 0x00BD
    Info (210040): SRAM Object File ./adrv9371x_a10gx_time_limited.sof contains time-limited megafunction that supports Intel FPGA IP Evaluation Mode feature -- Vendor: 0x6AF7, Product: 0xBCE1
    Info (210040): SRAM Object File ./adrv9371x_a10gx_time_limited.sof contains time-limited megafunction that supports Intel FPGA IP Evaluation Mode feature -- Vendor: 0x6AF7, Product: 0xBCEC
    Info: *******************************************************************
    Info: Running Quartus Prime Programmer
    Info: Command: quartus_pgm --no_banner --mode=jtag -o p;./adrv9371x_a10gx_time_limited.sof
    Info (213045): Using programming cable "USB-BlasterII [1-9]"
    Info (213011): Using programming file ./adrv9371x_a10gx_time_limited.sof with checksum 0x30E12536 for device 10AX115S2F45@1
    Info (209060): Started Programmer operation at Sun Oct 25 22:44:54 2020
    Info (209016): Configuring device index 1
    Info (209017): Device 1 contains JTAG ID code 0x02E660DD
    Info (209007): Configuration succeeded -- 1 device(s) configured
    Info (209011): Successfully performed operation(s)
    Info (209061): Ended Programmer operation at Sun Oct 25 22:45:08 2020
    Please enter i for info and q to quit:

    Here is output in nios2-terminal.

    $ nios2-download -r -g release.elf && nios2-terminal 
    Using cable "USB-BlasterII [1-9]", device 1, instance 0x00
    Resetting and pausing target processor: OK
    Initializing CPU cache (if present)
    OK
    Downloaded 409KB in 0.5s (818.0KB/s)
    Verified OK                         
    Starting processor at address 0x00000238
    nios2-terminal: connected to hardware target using JTAG UART on cable
    nios2-terminal: "USB-BlasterII [1-9]", device 1, instance 0
    nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
    
    Please wait...
    rx_device_clk_pll: FPLL PLL calibration OK (1400 us)
    tx_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_os_device_clk_pll: FPLL PLL calibration OK (1000 us)
    rx_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    tx_adxcvr: ATX PLL calibration OK (20 ms)
    tx_adxcvr: Lane 0 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 1 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 2 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 3 TX termination and VOD calibration OK (600 us)
    rx_os_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_os_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Calibrations completed successfully
    rx_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.882 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_jesd lane 0 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 49 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
    	K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x47, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    rx_jesd lane 1 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
    	K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x48, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    tx_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.882 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	SYNC~: deasserted
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.881 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd lane 0 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
    	K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x43, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    rx_os_jesd lane 1 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
    	K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x44, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    tx_dac: Successfully initialized (245761108 Hz)
    rx_adc: Successfully initialized (122880554 Hz)
    rx_obs_adc: Successfully initialized (245761108 Hz)
    Done
    

    Any assistance in resolving this would be much appreciate.

    Thanks.

  • 0
    •  Analog Employees 
    on Oct 27, 2020 10:04 AM 1 month ago in reply to Nickbiz

    I've moved this thread to the dedicated "Microcontroller no-OS Drivers" section.

    nios2-terminal is connecting to a JTAG UART (that is not exposed as a dev/tty*). We didn't investigate yet how to connect a libiio client to a JTAG UART interface.

    Dragos

  • Actually, I ran the command below in a normal terminal of the CentOS 7, not via nios2-terminal.

    $ iio_writedev -u serial:/dev/ttyUSB0,921600 -b 400 system_bd.sopcinfo 
    Unable to create IIO context serial:/dev/ttyUSB0,921600: Fun

    There are two cables connecting to the board: JTAG via micro USB and USB to I2C cable (DC1613A).

    I hope that I can connect a libiio client to the Arria 10 GX via any one of these cables.

  • 0
    •  Analog Employees 
    on Nov 4, 2020 7:27 AM 1 month ago in reply to Nickbiz

    You could try redirect stdin and stdout of nios2-terminal to a file and use that file and maybe use that file as serial device: community.intel.com/.../62850

  • Thanks for the suggestion. But according to discussions in the provided link, it is too slow for my project.