9009 jesd stay in CGS

I run no-os project on zc706+9009, why the jesd stay at CGS mode, it just been Data mode once in a while, may one time of 100 times try.

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    •  Analog Employees 
    on Oct 23, 2020 6:55 AM in reply to xlh

    Even if it's recommended, the external reference clock is not mandatory for receiving/transmitting some data. That is the reference for the AD9528's PLL1. PLL1 provides reference input clock cleanup with external VCXO. However, in this project, PLL2 should normally lock even without PLL1 being locked.

    When trying to build the no-OS, you get an error. Are you sure you are actually using the clean master branch? @amiclaus didn't see any issues.