I run no-os project on zc706+9009, why the jesd stay at CGS mode, it just been Data mode once in a while, may one time of 100 times try.
Hello. I use the profile what you provide, and in following picture the left one is the result of nothing changes, and the right one is the result after
externalSysref = 0, /* 0=use internal SYSREF, 1= use external SYSREF */ change 1 to 0 for I did not provide external sysref to it
How did you build your project?
Did you use these guides?
Even if it's recommended, the external reference clock is not mandatory for receiving/transmitting some data. That is the reference for the AD9528's PLL1. PLL1 provides reference input clock cleanup with external VCXO. However, in this project, PLL2 should normally lock even without PLL1 being locked.
When trying to build the no-OS, you get an error. Are you sure you are actually using the clean master branch? @amiclaus didn't see any issues.
hi, how to check the FPGA jesd settings with the jesd of 9009,from talise_config.c it can see that the framerA and framerB lanes are all 2 (2*M/F) (F=2*M/numberOfLanes), and how to caculate the lanes number of deframer?
and another confusion is in tx_jesd IP cores the num lanes is 4(does this parameter is wrong?) rx_jesd IP cores the num lanes is 2 the same as talise_config.c
You can check the ADRV9009 Transceiver evaluation tool for valid configuration of the JESD204 links.
Our default configuration and all profiles use 4 lanes for TX, 2 lanes for RX and 2 lanes for observation. Given that the number of channels for RX and TX and maximum rate is the same, this accounts for the fact that the bandwidth for TX is double than RX. In case of the observation, in order to get maximum bandwidth, a single observation channel can be enabled.