I run no-os project on zc706+9009, why the jesd stay at CGS mode, it just been Data mode once in a while, may one time of 100 times try.
Even if it's recommended, the external reference clock is not mandatory for receiving/transmitting some data. That is the reference for the AD9528's PLL1. PLL1 provides reference input clock cleanup…
Hello,
What version of HDL / No-OS are you using ?
Regards,
Adrian
2019-r1，if I must provide a sysref clk to 9009 externally?
For the single evaluation board you don't need to provide sysref clk externally.
The issue that I see is that the Rx and ORx jesd204 links are overclocked as they should run at maximum 6.6Gbps on the ZC706
how to fix it?
You'll need to use the QPLL for both RX/TX/ORx. I don't think we currently support this.
Moving to No-OS for additional comments.
This profile should work on ZC706: https://github.com/analogdevicesinc/no-OS/tree/master/projects/adrv9009/profiles/tx_bw100_ir122p88_rx_bw100_or122p88_orx_bw100_or122p88_dc122p88
Dragos
Hello. I use the profile what you provide, and in following picture the left one is the result of nothing changes, and the right one is the result after
externalSysref = 0, /* 0=use internal SYSREF, 1= use external SYSREF */ change 1 to 0 for I did not provide external sysref to it