I am working on a QPSK modulation/demod design based on No-OS reference design. I use the cyclic mode ON and it works as expected as far as I see at ILA. (Using the ZCU102 Rev1.1, FMCOMMS4, Vivado 2018.3)
I am sending the data with the array length 800( repeated 4 times ). Then QPSK demodulator IP gives me the original data with the length of 200. When I change the cyclic mode to 0, the program stucks at adc_capture(). In the adc_capture, the code stucks in the loop https://github.com/analogdevicesinc/no-OS/blob/cb0e05a17bd1aaff7ffc4e04f7e613dcec089346/ad9361/sw/platform_xilinx/adc_core.c#L297 .
The questions are:
1) How should I determine the integer parameter of the adc_capture( )?
2) I don't want to use the cyclic mode. How should I modify the program to transmit data whenever I want. Because the data transmission is rely on a condition in my system.
3) In the reference software project, there is mdelay(1000) code. What is the purpose of this part. Is it necessary to use, because 1000ms is a huge delay.
4) In the cyclic mode, the data are demodulated with no error but I see some clock pulses at fifo_wr_overflow and fifo_rd_overflow signals when the data are demodulated successfulfy. Are these a sign of a problem or is it an expected behavior of the program?
The length of one transfer should be multiple of the maximum between DMA_DATA_WIDTH_SRC and DMA_DATA_WIDTH_DEST - have a look here: https://github.com/analogdevicesinc/hdl/blob/master/projects/fmcomms2…
The length of one transfer should be multiple of the maximum between DMA_DATA_WIDTH_SRC and DMA_DATA_WIDTH_DEST - have a look here: https://github.com/analogdevicesinc/hdl/blob/master/projects/fmcomms2/common/fmcomms2_bd.tcl
In our example, the capture is delayed by 1 second so everything is ready and stable (AGC, RFDC Tracking, BasebandDC Tracking and RX Quadrature Tracking are enabled by default) by the time of saving the data. You can remove/adjust that.
This thread might help you regarding transmitting data in non-cyclic mode: https://ez.analog.com/fpga/f/q-a/84785/handling-irq-axi-dma-controller/96508#96508
I'm not sure about the internal signals. https://ez.analog.com/fpga/f/q-a is a better place for this question.