ad9361 all tx_tune rates faild

hi,

- we have a costume board with Zynq MPSoC US+ (ZU5EV) and AD9361

- the layout of LVDS BB Data BUS Traces isTUNED:   LENGTH = aprox. 1800mil  & TUNED = aprox 1mil

- we use hdl-master-2017r1 & no-OS-master-2017r1 as REFERENCE

-we also run first this 2 projects on a "Commerical/TESTED? HW" for REFERENCE:
         - SDR PicoZed / ADRV9361     [with Devices  => "Zynq7000" (7035) + ad9361]

         - ZCU102 + fmcomms2,           [with Devices  => ZynqUS+ (ZU9EG) + ad9361     (more close to our ZU5EV :) ) ]

and the two Tx & Rx Channel of the ad9361 commplite: dig_tune & initialize & work just fine

(we Transmitted QPSK signal from the Tx Channels & checked it at spectrum analyzer / Sampled Sine  Signal's at the Rx Channels and checked the samples at vivado chipscope + analyze from the samples the Channels dynamic params, like: ADC SNR & THD, with Matlab). it work fine!

- when we repeat This process on our costume board we get (all init parames at no-os sw main.c file are @ default value/no change!):

a. at the ad9361 init stage: all 3 Rx dig tune pass ok (@25, 40, 61.44M rates)

b.  but all 3 Tx dig tune Fail:

SAMPL CLK: 25000000 tuning: TX
  0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

SAMPL CLK: 40000000 tuning: TX
  0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

SAMPL CLK: 61440000 tuning: TX
  0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

SAMPL CLK: 61440000 tuning: TX
  0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

ad9361_dig_tune: Tuning TX FAILED!
ad9361_init : AD936x initialization error
Done.


c. because Rx dig tune seem to passed we also tried to run with - 

interface-tune-skip-mode digital_interface_tune_skip_mode = 1 (skip TX TUNE)

to check only the Rx channles:

- know ad9361 initialize success & the commends on ad9361 from PS_UART seem's to work

(For exp: we write & read the rx channels: rx_rf_bandwidth / rx_gc_mode / rx_lo_freq / rx_samp_freq etc...)

but when we inject SINE signal (just as we did with the ZCU+fmcomms HW) we get random noise at Rx1_I, Rx1_Q & Rx2_I, Rx2_Q samples...

so right know it seems that rx & tx channles don't work... :/

what are we missing?
Regards,
Abi.

 

 

  • 2 more thing:
    1. when we inject the SINE wave to the Rx channles we also check the ad9361 senes the correct power:
    we read the: rx1_rf_gain? / rx2_rf_gain? 
    and we get valid values (for exp: rx_rf_gain=10 for -10dBm signal, rx_rf_gain=21 for -20dBm signal etc...) 

    2. when we get the random noise samples from Rx channels @ chipscope we also check the: adc_valid & dac_valid signals:
    they are = constant @ '1' (high)  


    Abi.

  • 0
    •  Analog Employees 
    on Oct 19, 2020 9:18 AM 1 month ago in reply to Abi Babi

    Hi,

    Do you get any timing violations in your HDL design?
    What reference clock do you use for the AD9361(is it 40MHz)?
    Can you use a more recent release 2019_r1, there are a few commits on the ad9361_lvds interface since 2017_r1.

    Andrei

  • Thank U for fast replay Andrei !

    1. I don't get timing violations at vivado:
       - WNS:    0.667ns

       - TNS:     0ns

       - Num of Failling EndPoints:   0

    2. REF CLK:

    > the OSC-SRC in my PCB is: 20MHz TCXO 1ppm
    (i think better even then PicozedSDR "Y4" +-25ppm? & fmcomms2 "Y101" +-50ppm?) 
    > my ad9361 XTALP port is Not-Connected
    > the clk signal at XTALN (after the 20pF AC-Coupling) is ~300mVpp and the wave look's good and smooth 

     * 1st try: XTALN = 40MHz (my OSC-SRC x2 mul with FPGA PLL)

    main.c - reference_clk_rate = 40000000UL (Default)

     * 2nd try: XTALN = 20MHz (my OSC-SRC directly via FPGA [assign statement] without any PLL or other LOGIC in is way...)
    of course i change the main.c param - reference_clk_rate = 20000000UL

    2nd try get a litter better results at the - Rx tune rates
    but the same in Tx tune (nothing pass at 25/40/61M Tx tune) :\
        
    i also try another test with change the tune rate test at ad9361_conv.c file to 5MHz
    and also so at 5MHz all Tx Tune test's fail :\


    3.
    i try aslo with the ni-OS-2019r1 => results are the same (all Tx tune test fails)



    Abi.

  • 0
    •  Analog Employees 
    on Oct 21, 2020 7:03 AM 1 month ago in reply to Abi Babi

    Hi Abi,

    Have you also tried with a newer HDL?
    Adding to the discussion.

    Andrei

  • 0
    •  Analog Employees 
    on Oct 22, 2020 6:21 AM 1 month ago in reply to andrei_g

    The digital interface tuning process is described here: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation - if the same HDL/no-OS works on ADRV9361 and FMCOMMS2, I would verify the schematic/layout of your custom board.

    Dragos

  • Thank u for your reply,

    in my board/layout:
    the design main clock (rx_clk_in_p/n pins) does't connect to My Zynq MP SOC (ZU5EV)
    at GC (Global Clock)

    so in vivado:
    i keepet the constrain of the clock with:  -4 PERIOD (for: 4ns <> 250MHz rates)

    but i added a:
    SET_DEDICATED_CLOCK_ROUTE false

    in this state the VIVADO Implemention pass with no TIMING VIOLATIONS...


    is this can cause to dig Tx Tune to fail in all rates?
    (it's not supposet to fail only in high rates that close to 250MHz at the LVDS BUS?)

    Abi. 

  • +1
    •  Analog Employees 
    on Oct 22, 2020 7:21 PM 1 month ago in reply to Abi Babi

    Hello,

    Is it possible that the pin locations are not correctly described in the HDL for the TX pins  (data/clock and frame)?

    Regard,

    Adroam 

  • Thank you Adroam!

    u are right!, i cheeked again my costume board layout:
    the TX_FRAME_P/N LVDS pins ware swapped!

    Thankfully the ad9361 can swap each LVDS pair P<>N individualy 
    by using LVDS Invert Cntrol1&2 Regs (0x03D, 0x03E)
    i set the TX FRAME bit (0xFF, 0x0F ==> 0xFF, 0x4F) and it solved the problem!

    know also the tx_dig_tune test pass (@25, 40, 61.44 MSPS)  :)


    little/other Tip
    incresing the LVDS bias (amplitude) in the main.c of the no-OS (75 to 450mV)
    also improved the dig_tune results of the RX - LVDS BUS

    Thank u for all the useful help & support!!! 
    Regurds,
    Abi.