i was able to run the evaluation board and i have being working on understanding the code and configuration. i was able to run the fmcdaq2 on 1000 MSPS and i was able to see a output signal in iio oscilloscope. but i can not able to run the 600 MSPS.
AT 600 MSPS.
i have few questions can i change the adc bit values ? and what is the maximum (adc-device-clk.channel divider) value ? can i use 40 MSPS adc for example what is the minimum sampling frequency ?
Hi Ahmed,You should take a look at the datasheets of AD9680 and AD9144 the ADC respectively DAC devices on the daq2 board.For each one a minimum sampling rate is defined. I think in the screenshot you…
The minimum supported sampling rate should be 500MSPS.
If you want a lower sampling rate, you could implement a core that decimates the samples in the software or HDL.
If you want to run at 600 or 500 MSPS there are two options:
1. Keep the HDL that you are using at the moment and do ONLY a cherry pick on the no-os repo:
git cherry-pick 7980ad177a0d15849116d01417318c1730bf82f7
And rebuild the no-os project
2. Build the HDL from the master branch, do a pull on the no-os repo, and rebuild the no-os project with the new hdl.
Also, what do you mean by changing the adc bit values?
in the first time i ran no-OS i was able to run case 1 and 2 without any problem but now none of them works now i am getting this error i am so confused .
what i am trying to do is to just use the ADC and manipulate the configuration for example (sampling bit size = ad9680 (14-bit ) and sampling frequency i am looking for a sampling frequency of 35 MSPS.
can i do that changing in the channel.divider line in fmcdaq2.c
one more question can i save the ADC output "sampled data " to a file on my laptop ?
You asked about the 600 MSPS config and the previous changes were used for the 600 and 500 sampling rates.
The ad9680 is a 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS ADC. You can't set the sampling rate that low. In your case, in order to get 35 MSPS you can implement a software or hardware core that pics only the required samples from the data stream.
For the sample data, you can use: https://www.xilinx.com/html_docs/xilinx2019_1/SDK_Doc/SDK_tasks/sdk_t_memory_dump_restore.html.
There is a macro for the memory location where the data is stored (ADC_DDR_BASEADDR). You can follow the definition for this macro and find out the address that has to be introduced in the xilinx's memory utility.
i am asking this question because in the daq2 clocking guide he was able to set the sampling slow as 370 using division factor (ADC converter clock) cannot i use the same concept and increase the division settings;.
also how can i fix this error about setting up the evaluation broad:
error: ad9144_xcvr :adxcvr_clk_enable ().
Hi Ahmed,You should take a look at the datasheets of AD9680 and AD9144 the ADC respectively DAC devices on the daq2 board.For each one a minimum sampling rate is defined. I think in the screenshot you posted above, describes a setup for the minimum sampling rates.
After consulting the datasheets you might be required to change JESD parameters , like the number of lanes. Here you should modify the HDL design, if it is the case.The reference design is an example and it is tested at a limited number of sampling rates. If your custom design does not work for a particular sampling rate, You may have to change some transceiver parameters, for that you will need to play with the transceiver wizard, take a look at https://wiki.analog.com/resources/fpga/docs/xgt_wizard.
Not sure why you want to use daq2 for such a low sampling rate, keep in mind that it was a design for RF.
It will not work with low frequency signals. Take a look at:https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/22477/daq2-dac-output/179832#179832
Similar project, same DAC, related possible issue https://ez.analog.com/fpga/f/q-a/536630/ad9680-dc-coupling-daq3/392212#392212