AD9467 KC705 Reference design

Hello,

I've checked the latest version of the project from the master branch:
https://github.com/analogdevicesinc/no-OS/tree/master/ad9467-fmc-ebz

With the 2019_R1 HDL release for this project.

Using the common_drivers https://github.com/analogdevicesinc/no-OS/tree/master/common_drivers

(you will have to change the "#include "spi.h"" with "#include "platform_drivers.h"" in the ad9467.h and ad9517.h files, since the drivers are using a newer version of communication drivers)

I've checked multiple times the output and I did not get different results (as you mentioned in your case).

The output is always this one:

*****************************************************
  ADI AD9467-FMC-EBZ Reference Design
  AD9467 CHIP ID: 0x50
  AD9467 CHIP GRADE: 0x20
  AD9517 CHIP ID: 0xd3d3
*****************************************************
adc_setup adc core initialized (186 MHz).
                                         AD9467[0x016]: 00
adc_delay: setting zero error delay (28)
ADC Test: mode - MIDSCALE
          format - OFFSET BINARY
        Test passed
ADC Test: mode - MIDSCALE
          format - TWOS_COMPLEMENT
        Test passed
ADC Test: mode - POS_FULLSCALE
          format - OFFSET BINARY
        Test passed
ADC Test: mode - POS_FULLSCALE
          format - TWOS_COMPLEMENT
        Test passed
ADC Test: mode - NEG_FULLSCALE BINARY
          format - OFFSET BINARY
        Test passed
ADC Test: mode - NEG_FULLSCALE BINARY
          format - TWOS_COMPLEMENT
        Test passed
ADC Test: mode - CHECKERBOARD
          format - OFFSET BINARY
        Test passed
ADC Test: mode - CHECKERBOARD
          format - TWOS_COMPLEMENT
        Test passed
ADC Test: mode - PN_23_SEQUENCE
          format - OFFSET BINARY
          Test passed
ADC Test: mode - PN_23_SEQUENCE
          format - TWOS_COMPLEMENT
          Test skipped
ADC Test: mode - PN_9_SEQUENCE
          format - OFFSET BINARY
  ERROR: PN status(0002).
ADC Test: mode - PN_9_SEQUENCE
          format - TWOS_COMPLEMENT
          Test skipped
ADC Test: mode - ONE_ZERO_TOGGLE
          format - OFFSET BINARY
        Test passed
ADC Test: mode - ONE_ZERO_TOGGLE
          format - TWOS_COMPLEMENT
        Test passed
Testing done.
Start capturing data...

Done.

Also, the data in the memory (0x80800000) looks fine for the test modes (+ Full-scale, - Full-scale, Checkerboard).

Regards,

Antoniu

Hi Antoniu,

Thank you for the reply.
I tried to print the data as the following structure:

Addr |                        0x80800000                    |                         0x80800000 + 1                         | 
Data | D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]   |   D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] |

<sine>                                                                                              <square>

The waveform is more clean than before, but the waveform is still far from the ideal one

Could you give some advice?

Thanks

Wei-Chieh

Hi

Have you connected an external clock? https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467

Andrei

Hi

Have you connected an external clock? https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467

Andrei

Hi Andrei,

No, I only connect AIN.
Does the default setting of the no-os project and the default RTL should connect the externel clock?

Thanks
Wei-Chieh

Hi Wei-Chieh,

Wei-Chieh said:

Does the default setting of the no-os project and the default RTL should connect the externel clock?

Yes, as stated in the link I posted above.

Andrei

Hi Andrei,

I connect the 10MHz Sine Wave with 2.2Vpp 1.9Vdc as clock signal to sample the 100kHz 2.2Vpp 1.9Vdc analog source.
And I get the following waveform:
<sine 100kHz 2.2Vpp 1.9Vdc>                                                <square 100kHz 2.2Vpp 1.9Vdc>

The sine wave is great, but the square wave fail.

Thanks

Wei-Chieh

Hi Wei-Chieh,

As I said in the beginning of the thread, the input of the evaluation board is AC coupled not DC. This means it was not design to capture square waves(DC components).

Andrei

Hi Andrei,

Because I have only one function generator now, I want to sample data by AD9517.

And I have the following 2 questions:
1. Can I just short P200 and ON as the follwing picture to enable the clock input?

    Or I should weld some 0.1uF capacitors (C304, C305, C306, C307) and remove C209 and C210?

2. Can I switch to DC-coupling by adding 

     ad9467_analog_input_coupling(ad9467_device, 1, &status);
     ad9467_transfer(ad9467_device);

     in no-OS project?

Thanks,

Wei-Chieh

Hello,

P200 is used to disable the clock. If it's open, the clock is running (https://eu.mouser.com/datasheet/2/268/VCC6-1539124.pdf).

In the documentation pointed above: "The evaluation board can be set up to be clocked from the crystal oscillator, Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running."

If you want to use the AD9517 you could also do, on top of the above: "A differential LVPECL or LVDS clock driver can also be used to clock the ADC input using the AD9517. Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options."

Regarding the Analog Input, you can check the schematic page 1 for the analog input circuitry https://wiki.analog.com/_media/resources/fpga/xilinx/fmc/9467fmc01c_sch.pdf 

Regards,

Adrian