AD9361 Tuning TX FAILED error after upgrading Vivado 2018.2 to 2018.3 (no OS)

Hi all.

I am using the AD9361 & Zynq Z7035 Soc on the ADRV1CRR-FMC carrier, so standard off-the-shelf hardware, and no operating system (using bare metal).

Using the Vivado 2018.2 toolchain and the hdl_2018-r1 library, I could successfully compile & run my design, which uses both RX & both TX channels of the AD9361. Also, the FPGA compiled with no timing issues: total negative slack was 0ns and the number of failing endpoints was zero.

After installing Vivado 2018.3 and upgrading the project (i.e. the exact same FPGA design & AD9361 initialisation code), the FPGA now compiles with a total negative slack time of -105ns and 116 failing endpoints. Then when I run the design, I get the following AD9361 initialisation error:

SAMPL CLK: 61440000 tuning: TX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_dig_tune_delay: Tuning TX FAILED!
ad9361_init : AD936x initialization error

The other weird observation is that if I set two_rx_two_tx_mode_enable to 0 (only use a single RX channel) then I do not get the digital tuning error.

To avoid the error, I can set digital_interface_tune_skip_mode to 2 and skip the tuning. But I really would like to understand why/how upgrading Vivado causes such huge problems.

Regards

Mark

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