FMCOMMS3 ad9361_dig_tune_delay RX tuning problem

I am new to using FMCOMMS3/AD9361.  I'm using Vivado 2018.2, ZC706 with FMCOMMS3.  I downloaded no-OS 2018_R2 branch and HDL 2018_r2 branch.

I've built the HDL and the no-OS using Cygwin and make.  In both cases, I've built the ZC706 project under FMCOMMS2.

After no-OS make was successful, when I issue "make run" in Cygwin, the AD9361 device is successfully initialized, with the following output on Cygwin:

$ make run
xsdb.bat ../../../no-OS/scripts/xsdb.tcl ZYNQ_PS7
attempting to launch hw_server

****** Xilinx hw_server v2018.2
  **** Build date : Jun 14 2018-20:42:52
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application

****** Xilinx hw_server v2018.2

  **** Build date : Jun 14 2018-20:42:52

    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: hw_server application started

INFO: Use Ctrl-C to exit hw_server application

INFO: To connect to this hw_server instance use url: TCP:

100%    3MB   1.7MB/s  00:01
Downloading Program -- F:/Suneel/AD-No-OS-and-HDL/no-OS/fmcomms2/zc706/sw/Release/sw.elf
        section, .text: 0x00100000 - 0x00128cc7
        section, .init: 0x00128cc8 - 0x00128cdf
        section, .fini: 0x00128ce0 - 0x00128cf7
        section, .rodata: 0x00128cf8 - 0x0012eddb
        section, .data: 0x0012ede0 - 0x0012fd93
        section, .eh_frame: 0x0012fd94 - 0x0012fd97
        section, .mmu_tbl: 0x00130000 - 0x00133fff
        section, .ARM.exidx: 0x00134000 - 0x00134007
        section, .init_array: 0x00134008 - 0x0013400b
        section, .fini_array: 0x0013400c - 0x0013400f
        section, .bss: 0x00134010 - 0x00134487
        section, .heap: 0x00134488 - 0x0013648f
        section, .stack: 0x00136490 - 0x00139c8f
100%    0MB   0.4MB/s  00:00
Setting PC to Program Start Address 0x00100000
Successfully downloaded F:/Suneel/AD-No-OS-and-HDL/no-OS/fmcomms2/zc706/sw/Release/sw.elf

The console output of "make run" is as follows:

no-OS-make-run-Teraterm-Output - Copy.txt
ad9361_init : AD936x Rev 2 successfully initialized

Thereafter, "make capture" creates .csv files as it promises.

Next, I create a project in Xilinx SDK, by defining a new hardware platform and specifying the .hdf and bitstream files generated while making the HDL.  I import all the .c and .h files under the sw folder in the just-built no-OS project to the src folder in SDK.  SDK builds the project successfully.

I then open config.h and uncomment "#define XILINX_PLATFORM"

Then the auto-build is again successful.  But, when I try to run the program (GDB), I get the following output in console:

SAMPL CLK: 61440000 tuning: RX
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_dig_tune_delay: Tuning RX FAILED!
ad9361_init : AD936x initialization error

I did not make any changes to main.c or to any other file, except uncommenting "#define XILINX_PLATFORM" in config.h.

I downloaded and repeated the exercise with the "master" branch (both HDL and no-OS software) with identical results.

Setting digital_interface_tune_skip_mode to 2 makes the console output OK, but it is not the right thing to do.

If the HDL or hardware had a problem, I think the "make run" should also have thrown an error.  Since "make run" was OK, the HDL and hardware are is probably OK (or, are they?)

So, I must be missing something in the way the no-OS software is to be used, or something else is wrong.  What could be wrong?

Corrected the uploaded attachments. Added a few lines of explanation.
[edited by: cybersuneel at 1:21 PM (GMT 0) on 17 Jan 2020]
  • +1
    •  Analog Employees 
    on Jan 20, 2020 7:49 AM


    Try to also uncomment the "#define ADC_DMA_EXAMPLE" and make sure to power cycle the ZC706 as well.

    The second part is because the software might miss resetting some of the hardware cores.

    Let me know if this worked.


  • Dear Andreid1994,

    Thanks for your suggestion. Uncommenting #define ADC_DMA_EXAMPLE did NOT help.  But, as you said, it seems like some of the hardware (FPGA ?) was not being reset.  I was able to get the AD9361 to initialize successfully as follows:

    Originally, the carrier board was set to boot through QSPI Flash memory and was loading another FPGA bit-file and ELF at power-ON.  That state was probably not being fully reset. So, I set the carrier board to boot through JTAG.  Then, when the no-OS software was run for the first time, the AD9361 initialization was successful.  However, subsequent runs failed similar to the original failure

    Then, when I power cycled the carrier board, again the first run was successful with subsequent runs being failures.

    When I looked around, I found that in the run configurations (Run -> Run configurations) interface, "Reset Entire System" was left un-checked.  I checked "Reset Entire System" as shown below

    Once this was done, irrespective of whether #define ADC_DMA_EXAMPLE was commented or un-commented, AD9361 initialization was successful.

    Thanks, Andreid1994, and best wishes!

  • hi,

    I have checked with this option also yet getting the same message in the terminal

    ad9361_init : AD936x Rev 2 successfully initialized

    how can we get the list of commands in the terminal.


    Thyanks & regards


  • 0
    •  Analog Employees 
    on Oct 14, 2021 6:29 AM in reply to karthik.p207

    Hi Karthik,

    ad9361 initializes no matter what you define.

    After the initialization is done, two examples may be run depending on what you define:



    In the case of the first one, just observe the terminal output and possibly retrieve samples from memory with xilinx tools (documented on our wiki) and for the second example, you'd use iio-oscilloscope to view data. So no need for terminal commands.