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No-Os drivers DAC_DMA Example build problem

I have recently started using ADRV9009 Evaluation board along with ZC706 board (Plan to use with ZCU102 later by month end ).

I created the project cloning the sources from https://github.com/analogdevicesinc/hdl/ for both ZC706 and ZCU102 platforms and even downloaded the source codes from https://github.com/analogdevicesinc/hdl/ created the hw hw_bsp and sw project on XSDK and could compile properly.

Using https://github.com/analogdevicesinc/no-OS/blob/master/projects/adrv9009/src/app/headless.c as example code.

But if I uncomment DAC_DMA_EXAMPLE  from https://github.com/analogdevicesinc/no-OS/blob/master/projects/adrv9009/src/app/app_config.h this file to check the DMA example build fails with error "ad9528_gpio_param undeclared? Did you mean adi_hal_param"  and next error is "storage size of 'gpio_init_plddrbypass' is unknown"

Kindly suggest is I am missing any header or where gpio_init_plddrbypass gets defined?

Thanks in advance

Arun Kumar

Parents
  • Hi Arun,

    Thanks for the feedback, the adrv9009 DMA example was indeed broken by recent changes.

    Please see this pull request, you may use the commit of this pull request to be able to compile and play with the DMA example.

    https://github.com/analogdevicesinc/no-OS/pull/430

    Best regards,

    buha

  • Thank you for the reply.

    Now I am getting

    AD9528 SPI Read Verify failed (0x0)

    error: ad9528_setup() failed with (-1)

    on my console output

    How to solve this issue?

    is there any more changes required at gpio api i.e gpio.c and gpio.h

    Please suggest.

    Regards

    Arun Kumar

  • Hi again Arun,

    Here's the output that I am getting with a fresh no-OS master and 2019_r1 HDL branch https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r1

    It works well for me on ZC706 with ADRV9009-W/PCBZ. You may have an issue either with code version or maybe HDL image version.

    Regards,

    buha

    Hello
    rx_clkgen: MMCM-PLL locked (245760000 Hz)
    tx_clkgen: MMCM-PLL locked (245760000 Hz)
    rx_os_clkgen: MMCM-PLL locked (245760000 Hz)
    rx_adxcvr: OK (9830400 kHz)
    tx_adxcvr: OK (9830400 kHz)
    rx_os_adxcvr: OK (9830400 kHz)
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
    talise: Calibrations completed successfully
    rx_jesd: Lane 0 desynced (29 errors), restarting link
    rx_jesd: Lane 1 desynced (10 errors), restarting link
    rx_os_jesd: Lane 0 desynced (35 errors), restarting link
    rx_os_jesd: Lane 1 desynced (9 errors), restarting link
    rx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.779 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    tx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.779 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	SYNC~: deasserted
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.779 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    tx_dac: Successfully initialized (491558837 Hz)
    rx_adc: Successfully initialized (245779418 Hz)
    Bye
    

Reply
  • Hi again Arun,

    Here's the output that I am getting with a fresh no-OS master and 2019_r1 HDL branch https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r1

    It works well for me on ZC706 with ADRV9009-W/PCBZ. You may have an issue either with code version or maybe HDL image version.

    Regards,

    buha

    Hello
    rx_clkgen: MMCM-PLL locked (245760000 Hz)
    tx_clkgen: MMCM-PLL locked (245760000 Hz)
    rx_os_clkgen: MMCM-PLL locked (245760000 Hz)
    rx_adxcvr: OK (9830400 kHz)
    tx_adxcvr: OK (9830400 kHz)
    rx_os_adxcvr: OK (9830400 kHz)
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
    talise: Calibrations completed successfully
    rx_jesd: Lane 0 desynced (29 errors), restarting link
    rx_jesd: Lane 1 desynced (10 errors), restarting link
    rx_os_jesd: Lane 0 desynced (35 errors), restarting link
    rx_os_jesd: Lane 1 desynced (9 errors), restarting link
    rx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.779 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    tx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.779 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	SYNC~: deasserted
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.779 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    tx_dac: Successfully initialized (491558837 Hz)
    rx_adc: Successfully initialized (245779418 Hz)
    Bye
    

Children
  • I just get a fresh new download of 2019_r1 HDL and had the same error. Later I experienced there could be another reason for the following error: 

    AD9528 SPI Read Verify failed (0x0)

    error: ad9528_setup() failed with (-1)

    If in the run configuration "Reset entire system" has been checked you may get above error. As shown below uncheck it!

    Mamad

  • Hi , thanks for the feedback, looks good for now but if you still experience the issue after this, let me know here and I will try to reproduce and understand it.

  • Hi Buha,

    Would you please try DAC_DMA_Example by API and plot the received sine wave. I am not getting the expected sine wave on adrv9009/zc706.

    Thanks

  • Can you show us your initialization log messages?

    Thanks,
    Dragos

  • Please find it below.  

    Hello
    rx_clkgen: MMCM-PLL locked (245760000 Hz)
    tx_clkgen: MMCM-PLL locked (122880000 Hz)
    rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
    rx_adxcvr: OK (9830400 kHz)
    tx_adxcvr: OK (4915200 kHz)
    rx_os_adxcvr: OK (4915200 kHz)
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
    talise: Calibrations completed successfully
    rx_jesd: Lane 0 desynced (19 errors), restarting link
    rx_jesd: Lane 1 desynced (7 errors), restarting link
    rx_os_jesd: Lane 0 desynced (22 errors), restarting link
    rx_os_jesd: Lane 1 desynced (19 errors), restarting link
    rx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.764 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    tx_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.882 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	SYNC~: deasserted
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.882 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    tx_dac: Successfully initialized (245764160 Hz)
    rx_adc: Successfully initialized (245762634 Hz)

    Thanks for your help

  • The log looks good. How do you transfer the captured data to PC?

    Thanks,
    Dragos

  • Just reading from memory and print it out as below. 

    uint32_t *P2StartAdd = DDR_MEM_BASEADDR + 0x800000;
    memcpy(Data2Store_Test, P2StartAdd, (16384 * 8)/4);
    xil_printf("\n\n\n\n ******************** Rx data ******************** \n");
    for(int i=0; i< ((16384 * 8)/4) ; i++)
    {
    	xil_printf(" 0x%08x  ", Data2Store_Test[i]);
    	xil_printf("\n");
    }
     

  • Please note that in memory you should have 16384 samples, but 8 times more bytes since each sample requires 2 bytes and there are 4 channels: I0, Q0, I1, Q1.

    So, first 16 bytes will belong to I0, the next 16 bytes to Q0 and so one.

    Dragos

  • Thanks. I have considered the above fact you mentioned. Sometimes I receive just a noise. 

  • Don't forget to invalidate the cache memory (Xil_DCacheInvalidateRange()) after each DMA transfer to be sure you are reading the data from the actual main memory and not from the cache memory. Make sure the links are in DATA mode too.

    Dragos