ad9361 FMCOMMS2 RX data reception problem

hi.

TX board : Zynq706 & FMCOMMS2(ad9361) 

RX board : ZEDboard & FMCOMMS2(ad9361) use.

Tx data is sent normally.

Data sent from one board cannot be received from another board.

EVB board, target board AD9364 control does not receive the data sent

Using Matlab, TX and RX example samples were converted to HDL files. We confirmed that TX data is RX on Simulink.

However, PS implemented in SDK does not work properly.

The point where the actual RX data is not received is the RX stage coming out of the modem section of Vivado PL Logic.
Please check if the initial parameter is wrong, if there is a problem with the filter value, or if there is something to add on the PS.

 - Problem: EVB board (Zynq706 & FMCOMMS2 (AD9361)), (Zedboard & FMCOMMS2 (AD9361)) RX data receive X

 - Environment: Verifying by customizing NO-OS example source provided by ADI company based on baremetal (NO-OS)
   *  TDD MODE SETTING 
 - Transmitted data and received data are different




Source file (main.c): Please check if there is an incorrect setting.
   * Initial parameter value(AD9361_InitParam default_init_param)
   * filter value
   * FDD / TDD mode

   * delay
   * clock frequency

  
 
Currently estimated cause of the problem: RX_fir overflows at 0x035 value: Need a solution
The main.c file is shown below.

--------------------------------------------------------------------------------------------------------------------------------------------------------------------
/***************************************************************************//**
 *   @file   main.c
 *   @brief  Implementation of Main Function.
 *   @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
 * Copyright 2013(c) Analog Devices, Inc.
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  - Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  - Neither the name of Analog Devices, Inc. nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *  - The use of this software may or may not infringe the patent rights
 *    of one or more patent holders.  This license does not release you
 *    from the requirement that you obtain separate licenses from these
 *    patent holders to use this software.
 *  - Use of the software either in source or binary form, must be run
 *    on or directly connected to an Analog Devices Inc. component.
 *
 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/

/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include "config.h"
#include "ad9361_api.h"
#include "parameters.h"
#include "platform.h"
#ifdef CONSOLE_COMMANDS
#include "console_commands/command.h"
#include "console_commands/console.h"
#endif
#ifdef XILINX_PLATFORM
#include <xil_cache.h>
#endif
#if defined XILINX_PLATFORM || defined LINUX_PLATFORM || defined ALTERA_PLATFORM
#include "adc_core.h"
#include "dac_core.h"
#endif

#include <xil_io.h>


/******************************************************************************/
/************************ Variables Definitions *******************************/
/******************************************************************************/
#ifdef CONSOLE_COMMANDS
extern command          cmd_list[];
extern char            cmd_no;
extern cmd_function    cmd_functions[11];
unsigned char        cmd                 =  0;
double                param[5]         = {0, 0, 0, 0, 0};
char                param_no         =  0;
int                    cmd_type         = -1;
char                invalid_cmd         =  0;
char                received_cmd[30] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
#endif

AD9361_InitParam default_init_param = {
    /* Device selection */
    ID_AD9364,    // dev_sel
    /* Identification number */
    0,        //id_no
    /* Reference Clock */
    40000000UL,    //reference_clk_rate
    /* Base Configuration */
    0,        //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable
    1,        //one_rx_one_tx_mode_use_rx_num *** adi,1rx-1tx-mode-use-rx-num
    1,        //one_rx_one_tx_mode_use_tx_num *** adi,1rx-1tx-mode-use-tx-num
    0,        //frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable
    0,        //frequency_division_duplex_independent_mode_enable *** adi,frequency-division-duplex-independent-mode-enable
    1,        //tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable
    0,        //tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable
    0,        //tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns
    0,        //rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns
    0,        //rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable
    0,        //tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable
    0,        //external_rx_lo_enable *** adi,external-rx-lo-enable
    0,        //external_tx_lo_enable *** adi,external-tx-lo-enable
    5,        //dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask
    6,        //dc_offset_attenuation_high_range *** adi,dc-offset-attenuation-high-range
    5,        //dc_offset_attenuation_low_range *** adi,dc-offset-attenuation-low-range
    0x28,    //dc_offset_count_high_range *** adi,dc-offset-count-high-range
    0x32,    //dc_offset_count_low_range *** adi,dc-offset-count-low-range
    0,        //split_gain_table_mode_enable *** adi,split-gain-table-mode-enable
    MAX_SYNTH_FREF,    //trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz
    0,        // qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable
    /* ENSM Control */
    1,        //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable
    1,        //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable
    /* LO Control */
    2450000000UL,    //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz
    2450000000UL,    //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz
    1,                //tx_lo_powerdown_managed_enable *** adi,tx-lo-powerdown-managed-enable

    //khju_191007
    /* Rate & BW Control  Target Board */
    //{819200000, 102400000, 51200000, 25600000, 12800000, 6400000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
    //{819200000, 102400000, 51200000, 25600000, 12800000, 6400000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
    //6400000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
    //6400000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz


    /* Rate & BW Control  : ZED Board */
    {800011776, 25000368, 8333456, 4166728, 2083364, 520841},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
    {800011776, 25000368, 8333456, 4166728, 2083364, 520841},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
    434756,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
    1253625,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz
    /* RF Port Control */
    0,        //rx_rf_port_input_select *** adi,rx-rf-port-input-select                                                    //khju_191124 0 -> 1 -> 0    :physical port
    0,        //tx_rf_port_input_select *** adi,tx-rf-port-input-select                                                    //khju_191124 0 -> 1 -> 0    :physical port
    /* TX Attenuation Control */
    0,    //tx_attenuation_mdB *** adi,tx-attenuation-mdB
    0,        //update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable
    /* Reference Clock Control */
    0,        //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable
    //{6, 6017},    //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune
    {8, 5800},    //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune    Rx B'D {6, 6250}, Tx b'd {7, 6050}
    CLKOUT_DISABLE,    //clk_output_mode_select *** adi,clk-output-mode-select
    /* Gain Control */
    2,        //gc_rx1_mode *** adi,gc-rx1-mode
    2,        //gc_rx2_mode *** adi,gc-rx2-mode
    58,        //gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh
    4,        //gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size
    47,        //gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh
    8192,    //gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration
    0,        //gc_dig_gain_enable *** adi,gc-dig-gain-enable
    800,    //gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh
    704,    //gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh
    24,        //gc_low_power_thresh *** adi,gc-low-power-thresh
    15,        //gc_max_dig_gain *** adi,gc-max-dig-gain
    /* Gain MGC Control */
    2,        //mgc_dec_gain_step *** adi,mgc-dec-gain-step
    2,        //mgc_inc_gain_step *** adi,mgc-inc-gain-step
    0,        //mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable
    0,        //mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable
    0,        //mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode
    /* Gain AGC Control */
    10,        //agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter
    2,        //agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps
    0,        //agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable
    10,        //agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter
    4,        //agc_dig_gain_step_size *** adi,agc-dig-gain-step-size
    3,        //agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter
    1000,    // agc_gain_update_interval_us *** adi,agc-gain-update-interval-us
    0,        //agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable
    0,        //agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable
    10,        //agc_inner_thresh_high *** adi,agc-inner-thresh-high
    1,        //agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps
    12,        //agc_inner_thresh_low *** adi,agc-inner-thresh-low30720000
    1,        //agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps
    10,        //agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter
    2,        //agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps
    10,        //agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter
    5,        //agc_outer_thresh_high *** adi,agc-outer-thresh-high
    2,        //agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps
    18,        //agc_outer_thresh_low *** adi,agc-outer-thresh-low
    2,        //agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps
    1,        //agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us
    0,        //agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable
    /* Fast AGC */
    64,        //fagc_dec_pow_measuremnt_duration ***  adi,fagc-dec-pow-measurement-duration
    260,    //fagc_state_wait_tim


// khju_191113 Fixed GPIO Control _
#if 0 // GPIO Enable
#include "xgpiops.h"
#include "xscugic.h"
#include "xgpio.h"
#endife_ns ***  adi,fagc-state-wait-time-ns
    /* Fast AGC - Low Power */
    0,        //fagc_allow_agc_gain_increase ***  adi,fagc-allow-agc-gain-increase-enable
    5,        //fagc_lp_thresh_increment_time ***  adi,fagc-lp-thresh-increment-time
    1,        //fagc_lp_thresh_increment_steps ***  adi,fagc-lp-thresh-increment-steps
    /* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */
    1,        //fagc_lock_level_lmt_gain_increase_en ***  adi,fagc-lock-level-lmt-gain-increase-enable
    5,        //fagc_lock_level_gain_increase_upper_limit ***  adi,fagc-lock-level-gain-increase-upper-limit
    /* Fast AGC - Peak Detectors and Final Settling */
    1,        //fagc_lpf_final_settling_steps ***  adi,fagc-lpf-final-settling-steps
    1,        //fagc_lmt_final_settling_steps ***  adi,fagc-lmt-final-settling-steps
    3,        //fagc_final_overrange_count ***  adi,fagc-final-overrange-count
    /* Fast AGC - Final Power Test */
    0,        //fagc_gain_increase_after_gain_lock_en ***  adi,fagc-gain30720000-increase-after-gain-lock-enable
    /* Fast AGC - Unlocking the Gain */
    0,        //fagc_gain_index_type_after_exit_rx_mode ***  adi,fagc-gain-index-type-after-exit-rx-mode
    1,        //fagc_use_last_lock_level_for_set_gain_en ***  adi,fagc-use-last-lock-level-for-set-gain-enable
    1,        //fagc_rst_gla_stronger_sig_thresh_exceeded_en ***  adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable
    5,        //fagc_optimized_gain_offset ***  adi,fagc-optimized-gain-offset
    10,        //fagc_rst_gla_stronger_sig_thresh_above_ll ***  adi,fagc-rst-gla-stronger-sig-thresh-above-ll
    1,        //fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en ***  adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable
    1,        //fagc_rst_gla_engergy_lost_goto_optim_gain_en ***  adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable
    10,        //fagc_rst_gla_engergy_lost_sig_thresh_below_ll ***  adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll
    8,        //fagc_energy_lost_stronger_sig_gain_lock_exit_cnt ***  adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt
    1,        //fagc_rst_gla_large_adc_overload_en ***  adi,fagc-rst-gla-large-adc-overload-enable
    1,        //fagc_rst_gla_large_lmt_overload_en ***  adi,fagc-rst-gla-large-lmt-overload-enable
    0,        //fagc_rst_gla_en_agc_pulled_high_en ***  adi,fagc-rst-gla-en-agc-pulled-high-enable
    0,        //fagc_rst_gla_if_en_agc_pulled_high_mode ***  adi,fagc-rst-gla-if-en-agc-pulled-high-mode
    64,        //fagc_power_measurement_duration_in_state5 ***  adi,fagc-power-measurement-duration-in-state5
    /* RSSI Control */
    1,        //rssi_delay *** adi,rssi-delay
    1000,    //rssi_duration *** adi,rssi-duration
    3,        //rssi_restart_mode *** adi,rssi-restart-mode
    0,        //rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable
    1,        //rssi_wait *** adi,rssi-wait
    /* Aux ADC Control */
    256,    //aux_adc_decimation *** adi,aux-adc-decimation
    40000000UL,    //aux_adc_rate *** adi,aux-adc-rate
    /* AuxDAC Control */
    1,        //aux_dac_manual_mode_enable ***  adi,aux-dac-manual-mode-enable                                    khju_191117
    0,        //aux_dac1_default_value_mV ***  adi,aux-dac1-default-value-mV
    0,        //aux_dac1_active_in_rx_enable ***  adi,aux-dac1-active-in-rx-enable
    0,        //aux_dac1_active_in_tx_enable ***  adi,aux-dac1-active-in-tx-enable
    0,        //aux_dac1_active_in_alert_enable ***  adi,aux-dac1-active-in-alert-enable
    0,        //aux_dac1_rx_delay_us ***  adi,aux-dac1-rx-delay-us
    0,        //aux_dac1_tx_delay_us ***  adi,aux-dac1-tx-delay-us
    0,        //aux_dac2_default_value_mV ***  adi,aux-dac2-default-value-mV
    0,        //aux_dac2_active_in_rx_enable ***  adi,aux-dac2-active-in-rx-enable
    0,        //aux_dac2_active_in_tx_enable ***  adi,aux-dac2-active-in-tx-enable
    0,        //aux_dac2_active_in_alert_enable ***  adi,aux-dac2-active-in-alert-enable
    0,        //aux_dac2_rx_delay_us ***  adi,aux-dac2-rx-delay-us
    0,        //aux_dac2_tx_delay_us ***  adi,aux-dac2-tx-delay-us
    /* Temperature Sensor Control */
    256,    //temp_sense_decimation *** adi,temp-sense-decimation
    1000,    //temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms
    0xCE,    //temp_sense_offset_signed *** adi,temp-sense-offset-signed
    1,        //temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable
    /* Control Out Setup */
    0xFF,    //ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask
    0,        //ctrl_outs_index *** adi,ctrl-outs-index
    /* External LNA Control */
    0,        //elna_settling_delay_ns *** adi,elna-settling-delay-ns
    0,        //elna_gain_mdB *** adi,elna-gain-mdB
    0,        //elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB
    0,        //elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable
    0,        //elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable
    0,        //elna_gaintable_all_index_enable *** adi,elna-gaintable-a30720000ll-index-enable
    /* Digital Interface Control */
    0,        //digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode                            khju_191118
    0,        //digital_interface_tune_fir_disable *** adi,digital-interface-tune-fir-disable
    1,        //pp_tx_swap_enable *** adi,pp-tx-swap-enable
    1,        //pp_rx_swap_enable *** adi,pp-rx-swap-enable
    0,        //tx_channel_swap_enable *** adi,tx-channel-swap-enable                                            //khju_191124    0-> 1-> 0 : TX SWAP PORT 1,2
    0,        //rx_channel_swap_enable *** adi,rx-channel-swap-enable                                            //khju_191124    0-> 1-> 0 : RX SWAP PORT 1,2
    1,        //rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable
    0,        //two_t_two_r_timing_enable *** adi,2t2r-timing-enable
    0,        //invert_data_bus_enable *** adi,invert-data-bus-enable
    0,        //invert_data_clk_enable *** adi,invert-data-clk-enable
    0,        //fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable
    0,        //invert_rx_frame_enable *** adi,invert-rx-frame-enable
    0,        //fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable                                            //khju_191124
    0,        //swap_ports_enable *** adi,swap-ports-enable                                                    //khju_191124
    0,        //single_data_rate_enable *** adi,single-data-rate-enable        //khju_191126    defalut : 0
    1,        //lvds_mode_enable *** adi,lvds-mode-enable
    0,        //half_duplex_mode_enable *** adi,half-duplex-mode-enable            XXXXXXXX
    0,        //single_port_mode_enable *** adi,single-port-mode-enable        1 ok khju_191116
    0,        //full_port_enable *** adi,full-port-enable                        1 ok khju_191116
    0,        //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable
    4,        //delay_rx_data *** adi,delay-rx-data                            //khju_191126    defalut : 0
    0,        //rx_data_clock_delay *** adi,rx-data-clock-delay                //khju_191126    defalut : 0
    4,        //rx_data_delay *** adi,rx-data-delay                            //khju_191126    defalut : 4
    4,        //tx_fb_clock_delay *** adi,tx-fb-clock-delay                    //khju_191126    defalut : 7
    0,        //tx_data_delay *** adi,tx-data-delay
#ifdef ALTERA_PLATFORM
    300,    //lvds_bias_mV *** adi,lvds-bias-mV
#else
    150,    //lvds_bias_mV *** adi,lvds-bias-mV
#endif
    1,        //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable
    0,        //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable
    0xFF,    //lvds_invert1_control *** adi,lvds-invert1-control
    0x0F,    //lvds_invert2_control *** adi,lvds-invert2-control
    /* GPO Control */
    0,        //gpo0_inactive_state_high_enable *** adi,gpo0-inactive-state-high-enable
    0,        //gpo1_inactive_state_high_enable *** adi,gpo1-inactive-state-high-enable
    0,        //gpo2_inactive_state_high_enable *** adi,gpo2-inactive-state-high-enable
    0,        //gpo3_inactive_state_high_enable *** adi,gpo3-inactive-state-high-enable
    0,        //gpo0_slave_rx_enable *** adi,gpo0-slave-rx-enable
    0,        //gpo0_slave_tx_enable *** adi,gpo0-slave-tx-enable
    0,        //gpo1_slave_rx_enable *** adi,gpo1-slave-rx-enable30720000
    0,        //gpo1_slave_tx_enable *** adi,gpo1-slave-tx-enable
    0,        //gpo2_slave_rx_enable *** adi,gpo2-slave-rx-enable
    0,        //gpo2_slave_tx_enable *** adi,gpo2-slave-tx-enable
    0,        //gpo3_slave_rx_enable *** adi,gpo3-slave-rx-enable
    0,        //gpo3_slave_tx_enable *** adi,gpo3-slave-tx-enable
    0,        //gpo0_rx_delay_us *** adi,gpo0-rx-delay-us
    0,        //gpo0_tx_delay_us *** adi,gpo0-tx-delay-us
    0,        //gpo1_rx_delay_us *** adi,gpo1-rx-delay-us
    0,        //gpo1_tx_delay_us *** adi,gpo1-tx-delay-us
    0,        //gpo2_rx_delay_us *** adi,gpo2-rx-delay-us
    0,        //gpo2_tx_delay_us *** adi,gpo2-tx-delay-us
    0,        //gpo3_rx_delay_us *** adi,gpo3-rx-delay-us
    0,        //gpo3_tx_delay_us *** adi,gpo3-tx-delay-us
    /* Tx Monitor Control */
    37000,    //low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh
    0,        //low_gain_dB *** adi,txmon-low-gain
    24,        //high_gain_dB *** adi,txmon-high-gain
    0,        //tx_mon_track_en *** adi,txmon-dc-tracking-enable
    0,        //one_shot_mode_en *** adi,txmon-one-shot-mode-enable
    511,    //tx_mon_delay *** adi,txmon-delay
    8192,    //tx_mon_duration *** adi,txmon-duration
    2,        //tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain
    2,        //tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain
    48,        //tx1_mon_lo_cm *** adi,txmon-1-lo-cm
    48,        //tx2_mon_lo_cm *** adi,txmon-2-lo-cm
    /* GPIO definitions */
    -1,        //gpio_resetb *** reset-gpios
    /* MCS Sync */
    -1,        //gpio_sync *** sync-gpios
    -1,        //gpio_cal_sw1 *** cal-sw1-gpios
    -1,        //gpio_cal_sw2 *** cal-sw2-gpios
    /* External LO clocks */
    NULL,    //(*ad9361_rfpll_ext_recalc_rate)()
    NULL,    //(*ad9361_rfpll_ext_round_rate)()
    NULL    //(*ad9361_rfpll_ext_set_rate)()
};


AD9361_RXFIRConfig rx_fir_config = {    // BPF PASSBAND 3/20 fs to 1/4 fs

#if 0 // Target

    3, // rx
    0, // rx_gain
    4, // rx_dec
#else    //ZED
    3,
    -12,
    4,
#endif

#if 1    // ZEd
    {        /*434756*/
            197,   -86,   334,   -32,   238,   -99,   -39,  -369, -411, -648,
             -616,  -639,  -423,  -239,    70,   259,   419,   375,  241,  -46,
             -319,  -566,  -631,  -536,  -234,   148,   545,   785,  813,  560,
              108,  -447,  -907, -1137, -1007,  -543,   166,   896, 1427, 1543,
             1169,   353,  -680, -1629, -2157, -2044, -1223,   125, 1644, 2850,
             3295,  2695,  1057, -1286, -3705, -5422, -5683, -3981, -197, 5305,
            11735, 18010, 22998, 25758, 25758, 22998, 18010, 11735, 5305, -197,
            -3981, -5683, -5422, -3705, -1286,  1057,  2695,  3295, 2850, 1644,
              125, -1223, -2044, -2157, -1629,  -680,   353,  1169, 1543, 1427,
              896,   166,  -543, -1007, -1137,  -907,  -447,   108,  560,  813,
              785,   545,   148,  -234,  -536,  -631,  -566,  -319,  -46,  241,
              375,   419,   259,    70,  -239,  -423,  -639,  -616, -648, -411,
             -369,   -39,   -99,   238,   -32,   334,   -86,   197}, // rx_coef[128]

             /*1253625
               54,   -53,    39,  -124,  -126,  -316,  -401,  -580,  -647,  -710,
             -634,  -506,  -263,    -9,   255,   424,   491,   401,   201,   -84,
             -351,  -540,  -565,  -423,  -125,   234,   562,   737,   700,   429,
               -6,  -490,  -865, -1006,  -833,  -372,   266,   890,  1300,  1332,
              934,   177,  -733, -1523, -1915, -1729,  -942,   275,  1589,  2583,
             2878,  2251,   738, -1344, -3433, -4845, -4936, -3278,   204,  5174,
            10925, 16507, 20929, 23370, 23370, 20929, 16507, 10925,  5174,   204,
            -3278, -4936, -4845, -3433, -1344,   738,  2251,  2878,  2583,  1589,
              275,  -942, -1729, -1915, -1523,  -733,   177,   934,  1332,  1300,
              890,   266,  -372,  -833, -1006,  -865,  -490,    -6,   429,   700,
              737,   562,   234,  -125,  -423,  -565,  -540,  -351,   -84,   201,
              401,   491,   424,   255,    -9,  -263,  -506,   634,  -710,  -647,
             -580,  -401,  -316,  -126,  -124,   39 ,   -53,    54},*/

#else    // Target
     { 0, -1, -4, -8, -10, -5, 5, 12, 5, -10,
      -18, -5, 19, 27, 1, -34, -36, 9, 56, 43,
      -30, -84, -41, 66, 115, 25, -119, -142, 15, 188,
      155, -87, -267, -138, -196, 344, 76, -343,-400, 49,
      521, 409, -254, -714, -337, 549, 895, 145, -944, -1023,
      221, 1446, 1042, -842, -2083, -857, 1912, 2973, 237, -4124,
      -4726, 2047, 13752, 22890, 22890, 13752, 2047, -4726, -4124, 237,
      2973, 1912, -857, -2083, -842, 1042, 1446, 221, -1023, -944,
      145, 895, 549, -337, -714, -254, 409, 521, 49, -400,
      -343, 76, 344, -196, -138, -267, -87, 155, 188, 15,
      -142, -119, 25, 115, 66, -41, -84, -30, 43, 56,
      9, -36, -34, 1, 27, 19, -5, -18, -10, 5,
      12, 5, -5, -10, -8, -4, -1, 0
     },
#endif
     128, // rx_coef_size
     {0, 0, 0, 0, 0, 0}, //rx_path_clks[6]
     0 // rx_bandwidth
};

AD9361_TXFIRConfig tx_fir_config = {    // BPF PASSBAND 3/20 fs to 1/4 fs
#if 0 // Target
    3, // rx
    0, // rx_gain
    4, // rx_dec
#else    //ZED
    3,
    0,
    4,
#endif
#if 1    // ZED
    {
            /*197,   -86,   334,   -32,   238,   -99,   -39,  -369, -411, -648,
             -616,  -639,  -423,  -239,    70,   259,   419,   375,  241,  -46,
             -319,  -566,  -631,  -536,  -234,   148,   545,   785,  813,  560,
              108,  -447,  -907, -1137, -1007,  -543,   166,   896, 1427, 1543,
             1169,   353,  -680, -1629, -2157, -2044, -1223,   125, 1644, 2850,
             3295,  2695,  1057, -1286, -3705, -5422, -5683, -3981, -197, 5305,
            11735, 18010, 22998, 25758, 25758, 22998, 18010, 11735, 5305, -197,
            -3981, -5683, -5422, -3705, -1286,  1057,  2695,  3295, 2850, 1644,
              125, -1223, -2044, -2157, -1629,  -680,   353,  1169, 1543, 1427,
              896,   166,  -543, -1007, -1137,  -907,  -447,   108,  560,  813,
              785,   545,   148,  -234,  -536,  -631,  -566,  -319,  -46,  241,
              375,   419,   259,    70,  -239,  -423,  -639,  -616, -648, -411,
             -369,   -39,   -99,   238,   -32,   334,   -86,   197}, // tx_coef[128]
             */
               54,   -53,    39,  -124,  -126,  -316,  -401,  -580,  -647,  -710,
             -634,  -506,  -263,    -9,   255,   424,   491,   401,   201,   -84,
             -351,  -540,  -565,  -423,  -125,   234,   562,   737,   700,   429,
               -6,  -490,  -865, -1006,  -833,  -372,   266,   890,  1300,  1332,
              934,   177,  -733, -1523, -1915, -1729,  -942,   275,  1589,  2583,
             2878,  2251,   738, -1344, -3433, -4845, -4936, -3278,   204,  5174,
            10925, 16507, 20929, 23370, 23370, 20929, 16507, 10925,  5174,   204,
            -3278, -4936, -4845, -3433, -1344,   738,  2251,  2878,  2583,  1589,
              275,  -942, -1729, -1915, -1523,  -733,   177,   934,  1332,  1300,
              890,   266,  -372,  -833, -1006,  -865,  -490,    -6,   429,   700,
              737,   562,   234,  -125,  -423,  -565,  -540,  -351,   -84,   201,
              401,   491,   424,   255,    -9,  -263,  -506,   634,  -710,  -647,
             -580,  -401,  -316,  -126,  -124,   39 ,   -53,    54},
#else // TARGET
     // new filter kh_191001
     { 0, -1, -4, -8, -10, -5, 5, 12, 5, -10,
      -18, -5, 19, 27, 1, -34, -36, 9, 56, 43,
      -30, -84, -41, 66, 115, 25, -119, -142, 15, 188,
      155, -87, -267, -138, -196, 344, 76, -343,-400, 49,
      521, 409, -254, -714, -337, 549, 895, 145, -944, -1023,
      221, 1446, 1042, -842, -2083, -857, 1912, 2973, 237, -4124,
      -4726, 2047, 13752, 22890, 22890, 13752, 2047, -4726, -4124, 237,
      2973, 1912, -857, -2083, -842, 1042, 1446, 221, -1023, -944,
      145, 895, 549, -337, -714, -254, 409, 521, 49, -400,
      -343, 76, 344, -196, -138, -267, -87, 155, 188, 15,
      -142, -119, 25, 115, 66, -41, -84, -30, 43, 56,
      9, -36, -34, 1, 27, 19, -5, -18, -10, 5,
      12, 5, -5, -10, -8, -4, -1, 0
     },
#endif

     128, // tx_coef_size
     {0, 0, 0, 0, 0, 0}, // tx_path_clks[6]
     0 // tx_bandwidth
};
struct ad9361_rf_phy *ad9361_phy;
#ifdef FMCOMMS5
struct ad9361_rf_phy *ad9361_phy_b;
#endif


/***************************************************************************//**
 * @brief main
*******************************************************************************/
int main(void)
{
#ifdef XILINX_PLATFORM
    Xil_ICacheEnable();
    Xil_DCacheEnable();
#endif

#ifdef ALTERA_PLATFORM
    if (altera_bridge_init()) {
        printf("Altera Bridge Init Error!\n");
        return -1;
    }
#endif

    // NOTE: The user has to choose the GPIO numbers according to desired
    // carrier board.
    default_init_param.gpio_resetb = GPIO_RESET_PIN;
#ifdef FMCOMMS5
    default_init_param.gpio_sync = GPIO_SYNC_PIN;
    default_init_param.gpio_cal_sw1 = GPIO_CAL_SW1_PIN;
    default_init_param.gpio_cal_sw2 = GPIO_CAL_SW2_PIN;
    default_init_param.rx1rx2_phase_inversion_en = 1;
#else
    default_init_param.gpio_sync = -1;
    default_init_param.gpio_cal_sw1 = -1;
    default_init_param.gpio_cal_sw2 = -1;
#endif

#ifdef LINUX_PLATFORM
    gpio_init(default_init_param.gpio_resetb);
#else
    gpio_init(GPIO_DEVICE_ID);
#endif
    gpio_direction(default_init_param.gpio_resetb, 1);

    spi_init(SPI_DEVICE_ID, 1, 0);

    if (AD9364_DEVICE)
        default_init_param.dev_sel = ID_AD9364;
    if (AD9363A_DEVICE)
        default_init_param.dev_sel = ID_AD9363A;

#if defined FMCOMMS5 || defined ADI_RF_SOM || defined ADI_RF_SOM_CMOS
    default_init_param.xo_disable_use_ext_refclk_enable = 1;
#endif

#ifdef ADI_RF_SOM_CMOS
    default_init_param.swap_ports_enable = 1;
    default_init_param.lvds_mode_enable = 0;
    default_init_param.lvds_rx_onchip_termination_enable = 0;
    default_init_param.full_port_enable = 1;
    default_init_param.digital_interface_tune_fir_disable = 1;
#endif

    // calibration
    ad9361_spi_write(ad9361_phy->spi, REG_CALIBRATION_CTRL, 0x7B);


    ad9361_init(&ad9361_phy, &default_init_param);
    //xil_printf(" init end \r\n");

    ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);                // FILTER CEHCK !!!!!!
    //xil_printf(" ad9361_set_tx_fir_config end \r\n");

    ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
    //xil_printf(" ad9361_set_rx_fir_config end \r\n");

    //xil_printf(" axiLite_dac_init START \r\n");
    axiLite_dac_init(ad9361_phy);

    //xil_printf(" axiLite_dac_init END \r\n");


#ifdef FMCOMMS5
#ifdef LINUX_PLATFORM
    gpio_init(default_init_param.gpio_sync);
#endif
    gpio_direction(default_init_param.gpio_sync, 1);
    default_init_param.id_no = 1;
    default_init_param.gpio_resetb = GPIO_RESET_PIN_2;
#ifdef LINUX_PLATFORM
    gpio_init(default_init_param.gpio_resetb);
#endif
    default_init_param.gpio_sync = -1;
    default_init_param.gpio_cal_sw1 = -1;
    default_init_param.gpio_cal_sw2 = -1;
    default_init_param.rx_synthesizer_frequency_hz = 2300000000UL;
    default_init_param.tx_synthesizer_frequency_hz = 2300000000UL;
    gpio_direction(default_init_param.gpio_resetb, 1);
    ad9361_init(&ad9361_phy_b, &default_init_param);

    ad9361_set_tx_fir_config(ad9361_phy_b, tx_fir_config);
    ad9361_set_rx_fir_config(ad9361_phy_b, rx_fir_config);
#endif

#ifndef AXI_ADC_NOT_PRESENT
#if defined XILINX_PLATFORM || defined LINUX_PLATFORM || defined ALTERA_PLATFORM
#ifdef DAC_DMA_EXAMPLE
#ifdef FMCOMMS5
    dac_init(ad9361_phy_b, DATA_SEL_DMA, 0);
#endif

    ad9361_clock_Control_calib(ad9361_phy, 6);

    // ADD khju_191118

    ad9361_set_tx_fir_en_dis(ad9361_phy, 1);
    mdelay(1000);
    ad9361_set_rx_fir_en_dis(ad9361_phy, 1);
    mdelay(1000);
    ad9361_set_tx_sampling_freq(ad9361_phy, 520841);
    mdelay(1000);
    ad9361_set_rx_sampling_freq(ad9361_phy, 520841);

    dac_init(ad9361_phy, DATA_SEL_DMA, 1);


#else
#ifdef FMCOMMS5
    dac_init(ad9361_phy_b, DATA_SEL_DDS, 0);
#endif
    //dac_init(ad9361_phy, DATA_SEL_DDS, 1);

#endif
#endif
#endif

#ifdef FMCOMMS5
    ad9361_do_mcs(ad9361_phy, ad9361_phy_b);
#endif

#ifndef AXI_ADC_NOT_PRESENT
#if (defined XILINX_PLATFORM || defined ALTERA_PLATFORM) && \
    (defined ADC_DMA_EXAMPLE || defined ADC_DMA_IRQ_EXAMPLE)

    // NOTE: To prevent unwanted data loss, it's recommended to invalidate
    // cache after each adc_capture() call, keeping in mind that the
    // size of the capture and the start address must be alinged to the size
    // of the cache line.
    mdelay(1000);
    //xil_printf(" start adc_capture \r\n");
    adc_capture(8864, ADC_DDR_BASEADDR);
    //xil_printf(" end adc_capture \r\n");
#ifdef XILINX_PLATFORM
#ifdef FMCOMMS5
    Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 8864 * 16);
#else
    Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR,
            ad9361_phy->pdata->rx2tx2 ? 8864 * 8 : 8864 * 4);
#endif
#endif
#endif
#endif



    ad9361_clock_Control_calib(ad9361_phy, 6);

    // ADD khju_191118

    ad9361_set_tx_fir_en_dis(ad9361_phy, 1);
    mdelay(1000);
    ad9361_set_rx_fir_en_dis(ad9361_phy, 1);
    mdelay(1000);
    ad9361_set_tx_sampling_freq(ad9361_phy, 520841);
    mdelay(1000);
    ad9361_set_rx_sampling_freq(ad9361_phy, 520841);



    uint32_t ensm_mode;
    uint8_t reg_val;

//191125_TEST_VER FDD MODE

    dac_init(ad9361_phy, DATA_SEL_DMA, 1);

    ad9361_spi_write(ad9361_phy->spi, REG_ENSM_CONFIG_1, 0x11);            //0x69 changed    0x29 : not change
    ad9361_spi_write(ad9361_phy->spi, REG_ENSM_CONFIG_2, 0x04);

  
   /* TDD MODE SETTING */
    gpio_direction(GPIO_ENABLE_PIN, 1);
    gpio_direction(GPIO_TXNRX_PIN, 1);
    gpio_set_value(GPIO_ENABLE_PIN, 0);
    gpio_set_value(GPIO_TXNRX_PIN, 0);
    udelay(10);

    gpio_set_value(GPIO_ENABLE_PIN, 1);
    udelay(10);

    gpio_set_value(GPIO_ENABLE_PIN, 0);
    udelay(10);

    mdelay(1);

    gpio_set_value(GPIO_ENABLE_PIN, 1);
    udelay(10);

    gpio_set_value(GPIO_ENABLE_PIN, 0);
    udelay(10);

    mdelay(1);

    while(1)
    {
        reg_val = ad9361_spi_read(&ad9361_phy->spi, 0x014);
        console_print("register[0x014]=0x%2x\n", 0x014, reg_val);
        mdelay(1);

    }



#ifdef CONSOLE_COMMANDS

    get_help(NULL, 0);

    while(1)
    {
        console_get_command(received_cmd);
        invalid_cmd = 0;;
        for(cmd = 0; cmd < cmd_no; cmd++)
        {
            param_no = 0;
            cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
                                              param, &param_no);
            if(cmd_type == UNKNOWN_CMD)
            {
                invalid_cmd++;
            }
            else
            {
                cmd_list[cmd].function(param, param_no);
            }
        }
        if(invalid_cmd == cmd_no)
        {
            console_print("Invalid command!\n");
        }
    }
#endif

    printf("Done.\n");

#ifdef TDD_SWITCH_STATE_EXAMPLE
    uint32_t ensm_mode;
    if (!ad9361_phy->pdata->fdd) {
        if (ad9361_phy->pdata->ensm_pin_ctrl) {
            gpio_direction(GPIO_ENABLE_PIN, 1);
            gpio_direction(GPIO_TXNRX_PIN, 1);
            gpio_set_value(GPIO_ENABLE_PIN, 0);
            gpio_set_value(GPIO_TXNRX_PIN, 0);
            udelay(10);
            ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
            printf("TXNRX control - Alert: %s\n",
                    ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
            mdelay(1000);

            if (ad9361_phy->pdata->ensm_pin_pulse_mode) {
                while(1) {
                    gpio_set_value(GPIO_TXNRX_PIN, 0);
                    udelay(10);
                    gpio_set_value(GPIO_ENABLE_PIN, 1);
                    udelay(10);
                    //gpio_set_value(GPIO_ENABLE_PIN, 0);
                    ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                    printf("1 TXNRX Pulse control - RX: %s\n",
                            ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
                    mdelay(1000);

                    gpio_set_value(GPIO_ENABLE_PIN, 1);
                    udelay(10);
                    gpio_set_value(GPIO_ENABLE_PIN, 0);
                    ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                    printf("1 TXNRX Pulse control - Alert: %s\n",
                            ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
                    mdelay(1000);

                    gpio_set_value(GPIO_TXNRX_PIN, 1);
                    udelay(10);
                    gpio_set_value(GPIO_ENABLE_PIN, 1);
                    udelay(10);
                    gpio_set_value(GPIO_ENABLE_PIN, 0);
                    ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                    printf("1 TXNRX Pulse control - TX: %s\n",
                            ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
                    mdelay(1000);

                    gpio_set_value(GPIO_ENABLE_PIN, 1);
                    udelay(10);
                    gpio_set_value(GPIO_ENABLE_PIN, 0);
                    ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                    printf("1 TXNRX Pulse control - Alert: %s\n",
                            ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
                    mdelay(1000);
                }
            } else {
                while(1) {
                    gpio_set_value(GPIO_TXNRX_PIN, 0);
                    udelay(10);
                    gpio_set_value(GPIO_ENABLE_PIN, 1);
                    udelay(10);
                    ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                    printf("2 TXNRX control - RX: %s\n",
                            ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
                    mdelay(1000);

                    gpio_set_value(GPIO_ENABLE_PIN, 0);
                    udelay(10);
                    ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                    printf("2 TXNRX control - Alert: %s\n",
                            ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
                    mdelay(1000);

                    gpio_set_value(GPIO_TXNRX_PIN, 1);
                    udelay(10);
                    gpio_set_value(GPIO_ENABLE_PIN, 1);
                    udelay(10);
                    ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                    printf("2 TXNRX control - TX: %s\n",
                            ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
                    mdelay(1000);

                    gpio_set_value(GPIO_ENABLE_PIN, 0);
                    udelay(10);
                    ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                    printf("2 TXNRX control - Alert: %s\n",
                            ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
                    mdelay(1000);
                }
            }
        } else {
            while(1) {
                ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_RX);
                ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                printf("3 SPI control - RX: %s\n",
                        ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
                mdelay(1000);

                ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_ALERT);
                ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                printf("3 SPI control - Alert: %s\n",
                        ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
                mdelay(1000);

                ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_TX);
                ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                printf("3 SPI control - TX: %s\n",
                        ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
                mdelay(1000);

                ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_ALERT);
                ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
                printf("3 SPI control - Alert: %s\n",
                        ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
                mdelay(1000);
            }
        }
    }
#endif

#ifdef XILINX_PLATFORM
    Xil_DCacheDisable();
    Xil_ICacheDisable();
#endif

#ifdef ALTERA_PLATFORM
    if (altera_bridge_uninit()) {
        printf("Altera Bridge Uninit Error!\n");
        return -1;
    }
#endif

    return 0;
}

--------------------------------------------------------------------------------------------------------------------------------------------------------------------

Thank you.

  • 0
    •  Analog Employees 
    on Nov 29, 2019 8:41 AM 11 months ago

    Are you running Tx and Rx setup with same reference clock. ?

    It could be that frequency drift is impacting demodulation. May be you can try correcting the frequency error or give same reference clock to Tx and Rx.

    Moving this post to NO-OS for more comments.

  • thank you

    I'm testing with 1 board

    The Tx and Rx reference clocks are in the same state.

    How do I match my TX and RX settings?

  • +1
    •  Analog Employees 
    on Dec 12, 2019 6:16 PM 11 months ago in reply to BJang541

    Hi,

    The rx/tx_path_clock_frequencies specified in your default_init_param  are incorrect - they require an FIR filter (with a decimation/interpolation factor different than 1) to be enabled.

    Start with our default configuration and call the ad9361_trx_load_enable_fir() API after the initialization is done - it will enable the filters simultaneously and it will load the coefficients and the frequencies information too.

    Thanks,
    Dragos

  • I am using QPSK modem which is generated from MATLAB model like you. I am using same frequencies. I designed same filter by using AD9361 filter wizard. Can you transfer data successfully by using antennas or loopback sma cable? When I try to send data with ..hdl_loopback.. function demodulator successfully demodulate data. But when I go up to RF demodulator can not demodulate data. I didn't understand what is going on.

    furthermore If I set sampling frequencies as 520841 I can't use ILA. How did you handle with this?

    thanks