I have tested the software in development successfully and now making my custom board.
In my custom board some changes are there so i have to regenerate the u-boot-spl. I have followed the instruction given in analog devices wiki but i am getting error in Altera ARM DS-5 tool.
I am using windows7 OS also.
Please help me to overcome this issue.
Hi anki, Sorry for letting the conversation dry out, we missed it somehow. Is this issue still relevant ?
Hi DragosB No os software i am able to run in development board but in custom board it is not running. Difference between Dev board and custom board is that i am using only one SDRAM IC(512MB). How can i customize the driver software for custom board. I mean how can i generate u-boot-spl for custom board. I am facing problem while boot loader starts loading ad9361 .axf file to memory. please help me. regards anki
u-boot-spl is generated when the preloader/bootloader image is built (https://wiki.analog.com/resources/tools-software/linux-software/altera_soc_images#building_the_preloader_and_bootloader_image1) , so only updating the Quartus project should be enough.
i am getting below error while run in debugger(attached).
Where should i change, please help me.
Did you update the Quartus project according to your new memory chip specifications/connections?
I have updated in quartus project for single SDRAM IC.
J S hyanki
Not really. I would try to do a test by running Linux on this custom board as well.
Ok I will wait for your response.
FPGA hardware design (Modified with single SDRAM IC in QSYS) is ported in both boards(Dev Board & Custom Board) and in two conditions i have tested:
case 1: a) platform is custom board, u-boot-spl generated by me as per instruction given in adi site, No os provided by you same error is coming. attached earlier comment.
b) u-boot-spl provided by you, No os provided by you it hangs and DDR2 calibration fails and does not work at all.
case2: a) platform is dev board, u-boot-spl provided by you, no os provided by you, it is working fine, DDR2 calibration pass and showing 1024 MiB (Though in qsys it is 512MiB).
b)Platform is dev_board, u-boot-spl generated by me, no os provided by you, I am getting same error as in development board, DDR2 calibration pass and showing 512MiB.
I have two doubts now: I may missing something in u-boot-spl generation or two SDRAM (1024MB) is mandatory for HPS.
I am clueless now.
Please help me.
Anki, I was referring that you can do a test by running Linux on your custom board. Since it's not exactly an ADI issue, maybe you should ask Altera for some help on their forum as well.
you are right but I wanted to know that weather 512MiB memory is sufficient for AD9361 No OS software?
J S Hyanki
Yes, much less is actually required - have a look here: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/baremetal#code_size_information
It is showing maximum size 100KB. Its really surprising why it is not working.
Only U-Boot-SPL change is making differences. I am replacing U-Boot-SPL in Dev board. It is not working when i am using U-Boot-SPL generated by me.
what to do, I am stucked badly?
here Altera people are not able to help also.
I am attaching message, FPGA design & AD9361 software is same. I am changing u-boot-spl only.
please see the message. left one is corect which is running