AD9371 + KCU105 no-OS JESD setup fails with some profiles

We are testing a set of profiles on the AD9371 + KCU105 no-OS evaluation setup. All of these are generated with no errors using the AD9371 Filter Wizard. Two of these work on the hardware and two of them fail the JESD initialization.

These work:
1. full_rate profile - 122.88 MHz Tx, 122.88 MHz Rx
2. half_rate profile - 61.44 MHz Tx, 61.44 MHz Rx

But these two very similar profiles fail:
3. three_quarter_rate profile - 92.16 MHz Tx, 92.16 MHz Rx
4. three_eighths_rate profile - 46.08 MHz Rx, 46.08 MHz Rx

We're using a 122.88 MHz Device clock for all configurations.

Here's the configuration and console output for the full_rate profile that works:

Please wait...
rx_clkgen: MMCM-PLL locked (122880000 Hz)
tx_clkgen: MMCM-PLL locked (61440000 Hz)
rx_os_clkgen: MMCM-PLL locked (61440000 Hz)
MCS successful
CLKPLL locked
AD9371 ARM version 5.2.2
PLLs locked
Calibrations completed successfully
tx_adxcvr: OK (2457600 kHz)
rx_adxcvr: OK (4915200 kHz)
rx_os_adxcvr: OK (2457600 kHz)
RxFramerStatus = 0x3e
OrxFramerStatus = 0x3e
DeframerStatus = 0x28
rx_jesd status:
        Link is enabled
        Measured Link Clock: 122.881 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_jesd lane 0 status:
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 62 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x47, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
rx_jesd lane 1 status:
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 62 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x48, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
tx_jesd status:
        Link is enabled
        Measured Link Clock: 61.440 MHz
        Reported Link Clock: 61.440 MHz
        Lane rate: 2457.600 MHz
        Lane rate / 40: 61.440 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 61.440 MHz
        Reported Link Clock: 61.440 MHz
        Lane rate: 2457.600 MHz
        Lane rate / 40: 61.440 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd lane 0 status:
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 47 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x43, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 2457600 kHz
rx_os_jesd lane 1 status:
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 48 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x44, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 2457600 kHz
tx_dac: Successfully initialized (122879028 Hz)
rx_adc: Successfully initialized (122880554 Hz)
Done
Here's the configuration and console output for the three_quarter_rate profile that fails:
Please wait...
rx_clkgen: MMCM-PLL locked (92160000 Hz)
tx_clkgen: MMCM-PLL locked (46080000 Hz)
rx_os_clkgen: MMCM-PLL locked (46080000 Hz)
MCS successful
CLKPLL locked
AD9371 ARM version 5.2.2
PLLs locked
Calibrations completed successfully
tx_adxcvr: OK (1843200 kHz)
rx_adxcvr: OK (3686400 kHz)
rx_os_adxcvr: OK (1843200 kHz)
RxFramerStatus = 0x20
RxFramerStatus = 0x20
OrxFramerStatus = 0x20
OrxFramerStatus = 0x20
DeframerStatus = 0x61
DeframerStatus = 0x61
rx_jesd status:
        Link is enabled
        Measured Link Clock: 92.160 MHz
        Reported Link Clock: 92.160 MHz
        Lane rate: 3686.400 MHz
        Lane rate / 40: 92.160 MHz
        Link status: CGS
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_jesd lane 0 status:
        CGS state: INIT
        Initial Frame Synchronization: No
rx_jesd lane 1 status:
        CGS state: INIT
        Initial Frame Synchronization: No
tx_jesd status:
        Link is enabled
        Measured Link Clock: 46.080 MHz
        Reported Link Clock: 46.080 MHz
        Lane rate: 1843.200 MHz
        Lane rate / 40: 46.080 MHz
        SYNC~: deasserted
        Link status: ILAS
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 46.080 MHz
        Reported Link Clock: 46.080 MHz
        Lane rate: 1843.200 MHz
        Lane rate / 40: 46.080 MHz
        Link status: CGS
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd lane 0 status:
        CGS state: INIT
        Initial Frame Synchronization: No
rx_os_jesd lane 1 status:
        CGS state: INIT
        Initial Frame Synchronization: No
tx_dac: Successfully initialized (92160034 Hz)
rx_adc: Successfully initialized (92160034 Hz)
Done
As you can see, the JESD initialization is not complete. The RxFramerStatus and ORxFramerStatus are wrong. The link status never reaches the DATA state.
Can you try this failing configuration on your AD9371 + KCU105 setup? We're on an older tree (hdl_2018_r1), so I would like to know if this has been fixed since then. The myk.c files we used for these profiles are attached.
thanks.
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  • 0
    •  Analog Employees 
    on Jun 7, 2019 7:27 AM over 1 year ago

    Hi,

    Can you also show us the AD9528 configuration?

    Thanks,
    Dragos

  • The profiles including myk_ad9528init.c are attached. At the top level of each profile is the output from the AD9371 Filter Wizard along with a screen shot of the configuration. The TES folder has the script output from the Transceiver Evaluation Software. The eval folder has the myk.c and myk_ad9528init.c files used on the eval board, along with the console output.

    The Ref clock into the AD9528 on our eval board is 15.36 MHz (our signal generator is limited to 20 MHz). The Device Clock is set to 122.88 MHz. We're using the same myk_ad9528init.c file for both profiles:

    myk_ad9528init.c

    /* AD9528 data structure initialization file */
    #include <stdint.h>
    #include "common.h"
    #include "t_ad9528.h"
    
    static spiSettings_t clockSpiSettings =
    {
            1, //chip select Index
            0, //Write bit polarity
            1, //16bit instruction word
            1, //MSB first
            0, //Clock phase
            0, //Clock polarity
            0,//uint8_t enSpiStreaming;
            1,//uint8_t autoIncAddrUp;
            1 //uint8_t fourWireMode;
    };
    
    ad9528pll1Settings_t clockPll1Settings =
    {
        15360000,
        1,
        3,
        0,
        1,
        0,
        122880000,
        2,
        8
    };
    
    ad9528pll2Settings_t clockPll2Settings =
    {
        3,
        30
    };
    
    ad9528outputSettings_t clockOutputSettings =
    {
    	53237,
        {0,0,0,2,0,0,0,0,0,0,0,0,2,0},
        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
        {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
        {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
        {0,122880000,0,122880000,0,0,0,0,0,0,0,0,122880000,122880000}
    };
    
    ad9528sysrefSettings_t clockSysrefSettings =
    {
        0,
        2,
        0,
        0,
        0,
        0,
        512
    };
    
    ad9528Device_t clockAD9528_ =
    {
        &clockSpiSettings,
        &clockPll1Settings,
        &clockPll2Settings,
        &clockOutputSettings,
        &clockSysrefSettings
    };
    

    5873.profiles.zip

  • Have you guys had a chance to look at this? We would like to get these profiles working as configuration options for our customer.

    Thanks.

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