How to edit the talise_config.c file so it matches the output files from the Profile configuration wizard

Hi,

For generating a new profile, you have to use the ADRV9009 Transceiver Evaluation Software (https://www.analog.com/en/design-center/landing-pages/001/integrated-rf-agile-transceiver-design-resources.html). The dedicated EZ section that covers this application can be found here: https://ez.analog.com/wide-band-rf-transceivers/tes-gui-software-support-adrv9009-adrv9008-1-adrv9008-2/

Thanks,
Dragos

I did generate a new profile. So far so good...

<profile Talise version=1 name=Tx_BW200_IR240_Rx_BW196_OR240_ORx_BW200_OR240>
 <clocks>
  <deviceClock_kHz=240000>
  <clkPllVcoFreq_kHz=9600000>
  <clkPllHsDiv=2.5>
 </clocks>

 <rx name=Rx 196.00MHz, OutputRate 240.00MHz, TotalDecimation 8>
  <rxChannels=TAL_RX1RX2>
  <rxFirDecimation=2>
  <rxDec5Decimation=4>
  <rhb1Decimation=1>
  <rxOutputRate_kHz=240000>
  <rfBandwidth_Hz=196000000>
  <rxBbf3dBCorner_kHz=196000>
  <rxDdcMode=0>

  <rxNcoShifterCfg>
   <bandAInputBandWidth_kHz=0>
   <bandAInputCenterFreq_kHz=0>
   <bandANco1Freq_kHz=0>
   <bandANco2Freq_kHz=0>
   <bandBInputBandWidth_kHz=0>
   <bandBInputCenterFreq_kHz=0>
   <bandBNco1Freq_kHz=0>
   <bandBNco2Freq_kHz=0>
  </rxNcoShifterCfg>

  <filter FIR gain_dB=-6 numFirCoefs=48>
  -7, -26, 34, 54, -71, -118, 145, 216, -258, -372, 434, 601, -693, -940, 1073, 1443, -1642, -2238, 2548, 3643, -4327, -7191, 9306, 31148, 31148, 9306, -7191, -4327, 3643, 2548, -2238, -1642, 1443, 1073, -940, -693, 601, 434, -372, -258, 216, 145, -118, -71, 54, 34, -26, -7
  </filter>

  <rxAdcProfile num=42>
  189, 144, 176, 90, 1280, 948, 1331, 91, 1367, 46, 991, 19, 48, 48, 36, 209, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905
  </rxAdcProfile>
 </rx>

 <obsRx name=Rx 200.00MHz, OutputRate 240.00MHz, TotalDecimation 8>
  <obsRxChannelsEnable=TAL_ORX1ORX2>
  <enAdcStitching=0>
  <rxFirDecimation=2>
  <rxDec5Decimation=4>
  <rhb1Decimation=1>
  <orxOutputRate_kHz=240000>
  <rfBandwidth_Hz=200000000>
  <rxBbf3dBCorner_kHz=225000>
  <orxDdcMode=0>

  <filter FIR gain_dB=-6 numFirCoefs=48>
  -13, -37, 48, 67, -91, -138, 160, 206, -321, -388, 496, 612, -754, -936, 1129, 1409, -1686, -2158, 2580, 3502, -4313, -6856, 9459, 30776, 30776, 9459, -6856, -4313, 3502, 2580, -2158, -1686, 1409, 1129, -936, -754, 612, 496, -388, -321, 206, 160, -138, -91, 67, 48, -37, -13
  </filter>

  <orxLowPassAdcProfile num=42>
  187, 145, 177, 90, 1280, 980, 1334, 95, 1368, 48, 989, 18, 48, 48, 36, 209, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905
  </orxLowPassAdcProfile>

  <orxBandPassAdcProfile num=42>
  187, 145, 177, 90, 1280, 980, 1334, 95, 1368, 48, 989, 18, 48, 48, 36, 209, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905
  </orxBandPassAdcProfile>

 </obsRx>

 <lpbk>
  <rxFirDecimation=2>
  <rhb1Decimation=1>
  <outputRate_kHz=240000>
  <rfBandwidth_Hz=96000000>
  <rxBbf3dBCorner_kHz=225000>

  <filter FIR gain_dB=-6 num=48>
  -13
  -37
  48
  67
  -91
  -138
  160
  206
  -321
  -388
  496
  612
  -754
  -936
  1129
  1409
  -1686
  -2158
  2580
  3502
  -4313
  -6856
  9459
  30776
  30776
  9459
  -6856
  -4313
  3502
  2580
  -2158
  -1686
  1409
  1129
  -936
  -754
  612
  496
  -388
  -321
  206
  160
  -138
  -91
  67
  48
  -37
  -13
  </filter>

  <lpbkAdcProfile num=42>
  219, 143, 180, 90, 1280, 685, 1301, 58, 1340, 32, 885, 28, 48, 48, 33, 192, 0, 0, 0, 0, 48, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905
  </lpbkAdcProfile>
 </lpbk>

 <tx name=Tx 200.00MHz, InputRate 240.00MHz, TotalInterpolation 8>
  <txChannels=TAL_TX1TX2>
  <dacDiv=1>
  <txFirInterpolation=1>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <thb3Interpolation=2>
  <txInt5Interpolation=1>
  <txInputRate_kHz=240000>
  <primarySigBandwidth_Hz=96000000>
  <rfBandwidth_Hz=200000000>
  <txDac3dBCorner_kHz=200000>
  <txBbf3dBCorner_kHz=100000>

  <filter FIR gain_dB=0 numFirCoefs=20>
  35, -72, 106, -123, 115, -39, -233, 1073, -2923, 19948, -2923, 1073, -233, -39, 115, -123, 106, -72, 35, 0
  </filter>
 </tx>
</profile>

But how can I use it in the no-Os application?

The tool can directly create a no-OS profile: Tools - Create Script - Init .c Files

Dragos

Ah OK small miss understanding => I am using the www.analog.com/.../ADRV9008-x-ADRV9009-profile-config-tool-filter-wizard-v2.3.zip

With the tool you suggest, you can't change the sampling speed from 245.76MSPS to 240 MSPS.

And this tool didn't have that option...

OK, sorry for confusion. Aren't the lpbk FIR coefficients exactly the same as the obsRx ones? My assumption is that they are unused and they should be skipped. If I'm not wrong, we are doing the same on the Linux side (https://github.com/analogdevicesinc/linux/blame/master/drivers/iio/adc/adrv9009.c#L4326).

Thanks,
Dragos

My link status is CGS:

I am trying to change my sample rate to 240 MSPS. I have updated the talise_config.c file and the talise_config_AD9528.h. What could be the cause of the bad link status?

Hello
rx_clkgen: MMCM-PLL locked (240000000 Hz)
tx_clkgen: MMCM-PLL locked (120000000 Hz)
rx_os_clkgen: MMCM-PLL locked (120000000 Hz)
rx_adxcvr: OK (9600000 kHz)
tx_adxcvr: OK (4800000 kHz)
rx_os_adxcvr: OK (4800000 kHz)
talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
talise: Calibrations completed successfully
warning: TAL_DEFRAMER_A status 0x12
warning: TAL_FRAMER_A status 0x21
rx_jesd status:
        Link is enabled
        Measured Link Clock: 240.025 MHz
        Reported Link Clock: 240.000 MHz
        Lane rate: 9600.000 MHz
        Lane rate / 40: 240.000 MHz
        Link status: CGS
        SYSREF captured: Yes
        SYSREF alignment error: No
tx_jesd status:
        Link is enabled
        Measured Link Clock: 120.013 MHz
        Reported Link Clock: 120.000 MHz
        Lane rate: 4800.000 MHz
        Lane rate / 40: 120.000 MHz
        SYNC~: asserted
        Link status: CGS
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 120.012 MHz
        Reported Link Clock: 120.000 MHz
        Lane rate: 4800.000 MHz
        Lane rate / 40: 120.000 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_dac: Successfully initialized (240026855 Hz)
rx_adc: Successfully initialized (240025329 Hz)

My link status is CGS:

I am trying to change my sample rate to 240 MSPS. I have updated the talise_config.c file and the talise_config_AD9528.h. What could be the cause of the bad link status?

Hello
rx_clkgen: MMCM-PLL locked (240000000 Hz)
tx_clkgen: MMCM-PLL locked (120000000 Hz)
rx_os_clkgen: MMCM-PLL locked (120000000 Hz)
rx_adxcvr: OK (9600000 kHz)
tx_adxcvr: OK (4800000 kHz)
rx_os_adxcvr: OK (4800000 kHz)
talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
talise: Calibrations completed successfully
warning: TAL_DEFRAMER_A status 0x12
warning: TAL_FRAMER_A status 0x21
rx_jesd status:
        Link is enabled
        Measured Link Clock: 240.025 MHz
        Reported Link Clock: 240.000 MHz
        Lane rate: 9600.000 MHz
        Lane rate / 40: 240.000 MHz
        Link status: CGS
        SYSREF captured: Yes
        SYSREF alignment error: No
tx_jesd status:
        Link is enabled
        Measured Link Clock: 120.013 MHz
        Reported Link Clock: 120.000 MHz
        Lane rate: 4800.000 MHz
        Lane rate / 40: 120.000 MHz
        SYNC~: asserted
        Link status: CGS
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 120.012 MHz
        Reported Link Clock: 120.000 MHz
        Lane rate: 4800.000 MHz
        Lane rate / 40: 120.000 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_dac: Successfully initialized (240026855 Hz)
rx_adc: Successfully initialized (240025329 Hz)

Make sure the jesd204Settings (framers, deframers) from your new profile is the same as the one from our example. If you didn't change anything on the HDL side, also make sure that the both channels are enabled for RX and TX.

Thanks,
Dragos

I used following method to get started.

DragosB said:

The tool can directly create a no-OS profile: Tools - Create Script - Init .c Files

In this configuration the link status was "DATA".

Then I started updating the files to slave on the 120MHz VCO, to be able to sample at 240MSPS.  I didn't change any jesd204Settings (I think).

Only changes I made:

I still get bad Link status:

The error status that I get, changes from boot to boot:

warning: TAL_DEFRAMER_A status 0x12
warning: TAL_FRAMER_A status 0x21

or

warning: TAL_DEFRAMER_A status 0x13
warning: TAL_FRAMER_A status 0x21

In both cases I get " Link status: CGS" for rx_jesd and tx_jesd.

Where can I find more info about those statuses?

Have a look at the ADRV9008-1-W-9008-2-W-9009-W-Hardware-Reference-Manual-UG-1295. You should be able to find a description of TALISE_readDeframerStatus() and TALISE_readFramerStatus() functions.

Thanks,
Dragos

I have fond what the error means:

• SYSREF phase error, a new SYSREF had different timing than the first that set the LMFC timing.

Can you also point me what the rules are for SYSREF?

• I already checked the timing tH and tS on a oscillocope. SYSREF and REF_CLK are aligned how it should be aligned. (Valid sampling window)
• Do I have to recalculate the sysrefDivide as well (setting AD9528)? I changed my REF_CLK from 122,88MSPS to 120 MSPS? At this moment it is set to 512.

Different SYSREF divide factor value doesn't change the result...

2 questions:

1. The K divide factor is now set to 512. This will change my SYSREF clock frequency from 240KHz (122,88MHz VCO) to 234,375KHz(120MHz VCO). Could the extra decimal digits be a problem for the Talise package? Is this the reason why there is chosen for a 122,88 MHz crystal instead of an number like 120 MHz.
2. Is there an example talise_config.c file available with a deviceClock which is not from the list below? (if I divide those by 512, I always end up with less extra decimal digits compared to the 234,375KHz)
   

Hi JV-IE,

I see the original question was answered, you were able to generate talise_config.c using ADRV9009 Transceiver Evaluation Software by inputting into it the profile generated with the Talise Profile Configuration Wizard.

The discussion then switched topic to actually getting a working profile and then dried out, sorry for that. Being an old thread, is the 2nd discussion still valid ? If yes, I will split this conversation into a new thread.

Regards

I use the outputs from teh evaluation software to update : https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/adi-adrv9009.dtsi

I will not dynamically update profiles. I will use one fix profile.