I am working with zc706 and ADRV9371 evaluation boards. I'd like to transmit QAM4 data from transmitter end of the AD9371 with DMA mode on. According to "https://wiki.analog.com/resources/eval/user-guides/mykonos/software/basic_iq_datafiles" data is composed of In-phase and Quadrature parts. I am using only the TX1 path of the AD9371 and I assume the data file(LUT - array) to only composed of data related to TX1 path. Considering this and the following data :
In my case data is 32bits long and ı arranged my custom data according to sine_lut_iq and
(there was a already existing "const uint32_t sine_lut_iq" lut in NO_OS2018_R2).
However, after few trials, I observed that received data (both i and q parts) is only composed of q part of I/Q pairs. SO, I tried different methods to see the response of the system to IQ data;
After seeing results above, I couldn't conclude any cause to my problem. Apparently there is a problem but why this is problem is occuring is a mystery to me.
Lastly, I tried to see the example LUT included in No_OS 2018R2. As it seems, the lut is a sinus. If I run this LUT, ı would expect to see 2 signals (I and Q) with 90 degree phase difference. But what I see is following :
The Red is "I" part and blue is "Q" part. As you may see, they are nearly identical just like my own trials. I ınclude the "original" test LUT below.
As a result, I think that problem might be related to configuration of "IP core - AXI_AD9371_v1_0". There are registers to configure the format of IQ format as 2s complement or not. So, not configuring those registers might be a problem I believe.
Additional IMPORTANT Information: If I run the DDS mode, the I and Q values are different than each other as expected and resulting graph is a Sinusoidal.
Summary: I want to transmit a QAM signal with non-identical I and Q data (as it should be for QAM) but I observe the same identical data on I and Q parts of the received data. How can I solve it (My custom data is created according to const uint32_t sine_lut_iq" lut in NO_OS2018_R2 => 0x16bits_I_data+16bits_Q_data = 32bits in total).
Correction : In DDS mode, I and Q parts of the received data are also same. Sorry for misleading. I just conducted a new trial :)
Sorry for the late reply!
I assume you are using the ad9371 files from https://github.com/analogdevicesinc/no-OS/tree/master/ad9371/sw. This project is a bit outdated and will be removed soon.
Can you share your iq_rx1.csv generated file in DMA mode? Are you using VisualAnalog to plot the the received data? If so, make sure that from the Pattern Loader window, the I/Q - Interleaved File…
We will perform a test and come back to you.
Can you share your iq_rx1.csv generated file in DMA mode? Are you using VisualAnalog to plot the the received data? If so, make sure that from the Pattern Loader window, the I/Q - Interleaved File Format is selected.
Also, I assume that the setup was successful.
Looking forward to your answer!
Thank you for response in advance :)
1) The iq data is indeed generated in DMA mode, I am trying to use my custom data for modulation. Here is the iq_rx1.csv (used capture.tcl to be sure capturing is successful without doubt) .
(I couldnt upload the .csv format, so uploaded .txt version. Content is the same).
2) The results I have posted first is plotted by me on MATLAB. I was using 32 bit hex data and was processing that. But the "VisiualAnalog" gives the same results. You can see it below:
Thanks a lot.
Is there any progress or results related to tests you run?
I performed some tests and indeed there seem to be some issues caused by the hdl. I created a fix and a pull request to merge it to the master.
Until then, can you please try to perform a test using the project from this branch: https://github.com/analogdevicesinc/no-OS/tree/master-ad9371_dac_dma_example/projects/ad9371/src ? You need to import the app, devices and firmware folders in your project and also check the README for all the additional source files.
Please let me know how it goes!
Thank you very much.
I will perform the tests you advised urgently. Only problem of mine is, since I thought I am using the master branch of No-Os sw, ad9371 project would be the most recent project to use. I didn't even check the other files We found the problem anyways Thank you.
I have tried the NO-OS branch you wanted me to try and it didnt make a difference on the results.
I wanted to inform you. I and Q data are still the same.
On the hdl side, what branch are you using?
I am sorry for late reply. I am using HDL_2018_R2 revision of HDL.
Can you also perform a test using a Linux image? Here's our wiki page on how to get started: https://wiki.analog.com/resources/tools-software/linux-software/embedded_arm_images
I am sorry for this late response. I have some good news. Instead of testing the device with Linux image, I conducted new tests with UltraScale devices. The project I used for this purpose was built around example project given for ZCU102/AD9371 project. It seems lots of IP blocks used in ZCU102 differs from Zynq projects. So the results were also different. The Ultrascale projects functions perfectly. The error related to IQ data doesnt exist anymore. Most probably an IP block used in ZC706 example project might have some problems so it doesnt send I and Q data separately. I wanted to share my findings to support the process of solving existing problems.
Thank you very much for your interest. For me, case is closed
This is great! Thanks for letting us know!