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About enabling DPD when using ADRV 9375-W / PCBZ with Intel Arria 10 GX development kit

Hi

We have the design of Intel Arria 10 GX development kit using AD9371.
(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an792.pdf)

I would like to connect to ADRV9375-W / PCBZ using this design and try out the function of DPD.

I changed the source code with reference to the AD9371 Linux Driver and so on.

However, MYKONOS_waitInitCals () caused an error.

(If I do not add "DPD_INIT | CLGC_INIT | VSWR_INIT" to initCalMask, no error will occur.)

Specifically, it is CMB_SPIReadByte (device-> spiSettings, MYKONOS_ADDR_ARM_CMD_STATUS_ 0 + cmdByteIndex, & cmdByte); which is called in MYKONOS_readArmCmdStatusByte(),
This is because 224 is stored in cmdByte.

(It is 0 when it operates normally)

What does this mean?

Major Changed Code ]

< config_AD9371.c >

	uint32_t initCalMask = TX_BB_FILTER | ADC_TUNER | TIA_3DB_CORNER | DC_OFFSET |
	TX_ATTENUATION_DELAY | RX_GAIN_DELAY | FLASH_CAL |
	PATH_DELAY | TX_LO_LEAKAGE_INTERNAL | TX_QEC_INIT |
	LOOPBACK_RX_LO_DELAY | LOOPBACK_RX_RX_QEC_INIT |
	RX_LO_DELAY | RX_QEC_INIT
#ifdef AD9351
	| DPD_INIT | CLGC_INIT | VSWR_INIT ;
#else
	;
#endif

	printf("Mykonos RF Frequency setting Completed\n");
	/*************************************************************************/
	/*****                 Mykonos DPD Initialization                    *****/
	/*************************************************************************/
#ifdef AD9351
	if ((mykError = MYKONOS_configDpd(&mykDevice)) != MYKONOS_ERR_OK)
	{
	    /*** < Info: errorString will contain log error string in order to debug failure > ***/
	    errorString = getMykonosErrorMessage(mykError);
	}

	if ((mykError = MYKONOS_configClgc(&mykDevice)) != MYKONOS_ERR_OK)
	{
	    /*** < Info: errorString will contain log error string in order to debug failure > ***/
	    errorString = getMykonosErrorMessage(mykError);
	}

	if ((mykError = MYKONOS_configVswr(&mykDevice)) != MYKONOS_ERR_OK)
	{
	    /*** < Info: errorString will contain log error string in order to debug failure > ***/
	    errorString = getMykonosErrorMessage(mykError);
	}
	printf("Mykonos DPD Config Completed\n");
#endif
	/*************************************************************************/
	/*****                Mykonos Set GPIOs                              *****/
	/*************************************************************************/

< myk_config.c >

static mykonosTxSettings_t txSettings =
{
    &txProfile,     /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/
    &deframer,      /* Mykonos JESD204b deframer config for the Tx data path*/
    TX1,            /* The desired Tx channels to enable during initialization*/
    0,              /* Internal LO=0, external LO*2 if =1*/
    1000000000U,     /* Tx PLL LO frequency (internal or external LO)*/
    TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
    10000,          /* Initial and current Tx1 Attenuation mdB*/
    10000,          /* Initial and current Tx2 Attenuation mdB*/
    &dpdConfig,     /* <NULL>DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/
    &clgcConfig,    /* <NULL>CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
    &vswrConfig     /* <NULL>VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
};

Thanks and Regards,

Top Replies

Parents
  • Hi,

    What did you change in the source code? The Linux driver should support ADRV9375 without any change. However, it's true that we dind't test ADRV9375 on the Intel platforms.

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you for your support.

    I will answer your question.

    > What did you change in the source code?
    Basically my modified is only the above code.

    1. I added DPD_INIT, CLGC_INIT, VSWR_INIT to initCalMask.
    2. I added MYKONOS_configDpd(), MYKONOS_configClgc() and MYKONOS_configVswr() call after MYKONOS_setRfPllFrequency().
    3. I modified mykonosDpdConfig_t, mykonosClgcConfig_t, mykonosVswrConfig_t which is a member of static mykonosTxSettings_t txSettings from NULL to a pointer.

    Other than that, "Mykonos API version" has been replaced from "1.2.05.3518" to "1.5.2.3566".
    (In addition, Mykonos M3.bin has also been replaced.)

    > The Linux driver should support ADRV9375 without any change.
    I do not use Linux in my evaluation environment.
    It is a no-OS environment using Nios II.
    The reason for writing "source code with reference to the AD9371 Linux Driver" in the above description is because we could not find the code using DPD with no-OS.
    Thanks and Regards,
    Taka
  • Ok, I will move the thread to the corresponding place.

    Thanks,
    Dragos

  • We will add these days Altera support to https://github.com/analogdevicesinc/no-OS/tree/master/projects/ad9371/src (everything needed for the project - API, firmware - is included) - it would be better to start from this no-OS version instead of the original one (https://github.com/analogdevicesinc/no-OS/tree/master/ad9371/sw).

    We will let you know when it's be ready.

    Thanks,
    Dragos

  • The described changes were added: https://github.com/analogdevicesinc/no-OS/tree/ad9371_altera - they will be merged on master soon.

    Ca you do a test using this version?

    We'll try to also add support for ADRV9375.

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you for your support.

    I checked the downloaded source code.

    As a result, I couldn't get it to work well.

    So I have four questions.

    (1) Is the FPGA design correct at github.com/.../a10gx ?

    (2) I added files in the following folder to the Nios II Project. Is this correct?

    github.com/.../src
    github.com/.../drivers

    (3) In Nios II BSP-Editor's Linker Script, everything except .entry is DDR3. Do you need to change it?

    (4) It seems that processing related to DPD is not implemented in the source code, but specifically where does DPD related processing exist?

    Thanks and Regards,
    Taka
  • Hi,

    1. https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9371x/a10gx - this is the right project - make sure to disable the MMU for the no-OS setup - https://wiki.analog.com/resources/fpga/docs/build#alterabuild_your_desired_project

    2. You need the files specified in the README file.

    3. No changes are required to the default linker script.

    4. We merged the previous changes to master. The AD9375 ones are located on a dedicated branch: https://github.com/analogdevicesinc/no-OS/tree/ad9375/projects/ad9371/src

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you for your support.

    And I am sorry again and again.

    I tested the downloaded source code.

    As a result, I couldn't get it to work well.

    I will show you my evaluation environment.

    (Q1) I'm connecting like this, is there any problem?

    I operated as follows.

    (1) I added the file described in the README to the newly created Nios II project and executed it.

    Nios II Console Output Results ]

    Please wait...
    WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.
    rx_device_clk_pll: FPLL PLL calibration OK (1200 us)
    tx_device_clk_pll: FPLL PLL calibration OK (1000 us)
    rx_os_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    tx_adxcvr: ATX PLL calibration OK (20 ms)
    tx_adxcvr: Lane 0 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 1 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 2 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 3 TX termination and VOD calibration OK (600 us)
    rx_os_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_os_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    device->tx->dpdConfig structure has NULL pointer in MYKONOS_configDpd()

    (Q2) It was output as "WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.". Is there a problem?

    (2) Because "device->tx->dpdConfig structure has NULL pointer in MYKONOS_configDpd()" was output, in myk.c
    changed mykonosDpdConfig_t, mykonosClgcConfig_t, and mykonosVswrConfig_t from NULL to a structure pointer.

    static mykonosTxSettings_t txSettings =
    {
        &txProfile,     /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/
        &deframer,      /* Mykonos JESD204b deframer config for the Tx data path*/
        TX1_TX2,        /* The desired Tx channels to enable during initialization*/
        0,              /* Internal LO=0, external LO*2 if =1*/
        2500000000U,    /* Tx PLL LO frequency (internal or external LO)*/
        TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
        10000,          /* Initial and current Tx1 Attenuation mdB*/
        10000,          /* Initial and current Tx2 Attenuation mdB*/
        &dpdConfig,           /* DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/
        &clgcConfig,           /* CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
        &vswrConfig            /* VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
    };

    (3) I tried to run again.

    [ Nios II Console Output Results ]

    Please wait...
    WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.
    rx_device_clk_pll: FPLL PLL calibration OK (800 us)
    tx_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_os_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    tx_adxcvr: ATX PLL calibration OK (20 ms)
    tx_adxcvr: Lane 0 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 1 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 2 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 3 TX termination and VOD calibration OK (600 us)
    rx_os_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_os_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Unknown error was encountered.

    It seems that an error occurred in MYKONOS_waitInitCals ().
    The return value was MYKONOS_ERR_WAIT_INITCALS_CALFAILED.

    (Q3) What kind of problems can be considered as the cause of not working properly?

    Thanks and Regards,
    Taka

  • Hi,

    The  AD9528_initialize() warning can be caused by an improper/nonexistent clock connected to REF_CLK_IN (in our reference design, a clock of 30.72 MHz needs to be provided).

    Your changes to the txSettings are correct.

    By the way, can you also do a test by treating your AD9375 as a AD9371 (set prodid to AD9371_PRODID)?

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you for your answer.

    > in our reference design, a clock of 30.72 MHz needs to be provided.

    Thank you for your advice.

    The input frequency has been changed to 30.72 MHz.

    WARNING has disappeared, but the error in MYKONOS_waitInitCals () has not changed as before.

    > By the way, can you also do a test by treating your AD9375 as a AD9371 (set prodid to AD9371_PRODID)?

    I changed line 71 of headless.c and made it work.

    //#define AD9371_PRODID		0x03
    #define AD9371_PRODID		0x06
    #define IS_AD9371(prodid)	(prodid == AD9371_PRODID)

    When operating as an AD9371, no errors appear to occur.

    [ Nios II Console Output Results ]

    Please wait...
    rx_device_clk_pll: FPLL PLL calibration OK (1000 us)
    tx_device_clk_pll: FPLL PLL calibration OK (1000 us)
    rx_os_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    tx_adxcvr: ATX PLL calibration OK (20 ms)
    tx_adxcvr: Lane 0 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 1 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 2 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 3 TX termination and VOD calibration OK (600 us)
    rx_os_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_os_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Calibrations completed successfully
    rx_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.881 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_jesd lane 0 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
    	K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x47, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    rx_jesd lane 1 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
    	K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x48, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    tx_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.881 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	SYNC~: deasserted
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.881 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd lane 0 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
    	K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x43, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    rx_os_jesd lane 1 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 49 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
    	K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x44, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    tx_dac: Successfully initialized (245761108 Hz)
    rx_adc: Successfully initialized (122880554 Hz)
    Done

    Are there any other possible causes?

    Thanks and Regards,
    Taka

  • Hi Taka,

    This is good.

    I've added a small change to the ad9375 branch (https://github.com/analogdevicesinc/no-OS/tree/ad9375/projects/ad9371/src) - call MYKONOS_radioOff() before configuring DPD, CLGC andVSWR. However, I'm not sure if it helps since my assumption is that the Radio is anyway OFF at that moment. Unfortunately, I wasn't able to test this - I'm waiting for a ADRV9375 board.

    You can also have a look at our Linux driver (https://github.com/analogdevicesinc/no-OS/commit/455a34c91020241bb65149b4734c11ef835a5b8c) - the AD9375 driver support was tested over there.
    We also have an ADRV9371 device tree for Arria 10 GX - the only required change if ADRV9375 is used would to update the compatible string (compatible = "ad9375" instead of compatible = "ad9371") - https://github.com/analogdevicesinc/linux/blob/altera_4.9/arch/nios2/boot/dts/a10gx_adrv9371.dts#L285
    If you want to give it a try, we can give some instructions.

    Thanks,
    Dragos

Reply Children
  • Hi. Dragos

    Thank you for your answer.

    > Unfortunately, I wasn't able to test this - I'm waiting for a ADRV9375 board.

    I hope the ADRV9375 board will reach you fast...

    > call MYKONOS_radioOff() before configuring DPD, CLGC andVSWR. 

    I checked the operation, but still I got an error in the same place.

    [ Nios II Console Output Results ]

    Please wait...
    rx_device_clk_pll: FPLL PLL calibration OK (1200 us)
    tx_device_clk_pll: FPLL PLL calibration OK (1000 us)
    rx_os_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    tx_adxcvr: ATX PLL calibration OK (20 ms)
    tx_adxcvr: Lane 0 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 1 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 2 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 3 TX termination and VOD calibration OK (600 us)
    rx_os_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_os_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Unknown error was encountered.

    > If you want to give it a try, we can give some instructions.
    I do not plan to implement Linux, but I checked it by referring to the following page for reference.
    https://wiki.analog.com/resources/tools-software/linux-build/generic/nios2

    [ NiosII Command Shell ]

    $ nios2-configure-sof adrv9371x_a10gx.sof
    Searching for SOF file:
    in .
      adrv9371x_a10gx.sof
    
    Info: *******************************************************************
    Info: Running Quartus Prime Programmer
    Info: Command: quartus_pgm --no_banner --mode=jtag -o p;adrv9371x_a10gx.sof
    Info (213045): Using programming cable "USB-BlasterII [USB-1]"
    Info (213011): Using programming file adrv9371x_a10gx.sof with checksum 0x31451F
    EE for device 10AX115S2F45@1
    Info (209060): Started Programmer operation at Tue Apr 02 10:06:37 2019
    Info (209016): Configuring device index 1
    Info (209017): Device 1 contains JTAG ID code 0x02E060DD
    Info (209007): Configuration succeeded -- 1 device(s) configured
    Info (209011): Successfully performed operation(s)
    Info (209061): Ended Programmer operation at Tue Apr 02 10:06:52 2019
    Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
        Info: Peak virtual memory: 1489 megabytes
        Info: Processing ended: Tue Apr 02 10:06:52 2019
        Info: Elapsed time: 00:00:34
        Info: Total CPU time (on all processors): 00:00:27
    
    
    $ nios2-download -g vmlinux && nios2-terminal
    Using cable "USB-BlasterII [USB-1]", device 1, instance 0x00
    Pausing target processor: OK
    Initializing CPU cache (if present)
    OK
    Downloaded 8243KB in 10.9s (756.2KB/s)
    Verified OK
    Starting processor at address 0xC0000000
    nios2-terminal: connected to hardware target using JTAG UART on cable
    nios2-terminal: "USB-BlasterII [USB-1]", device 1, instance 0
    nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
    
    Linux version 4.9.0-g1d0d40c (altima@u11399-ubuntu14) (gcc versioclocksource: Sw
    itched to clocksource nios2-clksrc
    NET: Registered protocol family 2
    TCP established hash table entries: 2048 (order: 1, 8192 bytes)
    TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
    TCP: Hash tables configured (established 2048 bind 2048)
    UDP hash table entries: 256 (order: 0, 4096 bytes)
    UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
    NET: Registered protocol family 1
    RPC: Registered named UNIX socket transport module.
    RPC: Registered udp transport module.
    RPC: Registered tcp transport module.
    RPC: Registered tcp NFSv4.1 backchannel transport module.
    random: fast init done
    futex hash table entries: 256 (order: -1, 3072 bytes)
    workingset: timestamp_bits=30 max_order=16 bucket_order=0
    jffs2: version 2.2. (NAND) ツゥ 2001-2006 Red Hat, Inc.
    Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
    io scheduler noop registered
    io scheduler deadline registered
    io scheduler cfq registered (default)
    101814f0.serial: ttyJ0 at MMIO 0x101814f0 (irq = 2, base_baud = 0) is a Altera J
    TAG UART
    console [ttyJ0] enabled
    console [ttyJ0] enabled
    bootconsole [early0] disabled
    bootconsole [early0] disabled
    loop: module loaded
    spi_altera 10181400.spi: base f0181400, irq 8
    libphy: Fixed MDIO Bus: probed
    libphy: altera_tse: probed
    altera_tse 10181000.ethernet (unnamed net_device) (uninitialized): MDIO bus alte
    ra_tse-0: created
    altera_tse 10181000.ethernet: Altera TSE MAC version 18.1 at 0x10181000 irq 1/3
    mousedev: PS/2 mouse device common for all mice
    ad9371 spi32766.1: ad9371_probe : enter
    altera-a10-fpll 10045000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
    altera-a10-fpll 10035000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
    altera-a10-fpll 10025000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
    altera_adxcvr 10024000.axi-ad9371-tx-xcvr: ATX PLL calibration OK (20 ms)
    altera_adxcvr 10024000.axi-ad9371-tx-xcvr: Lane 0 TX termination and VOD calibra
    tion OK (500 us)
    altera_adxcvr 10024000.axi-ad9371-tx-xcvr: Lane 1 TX termination and VOD calibra
    tion OK (500 us)
    altera_adxcvr 10024000.axi-ad9371-tx-xcvr: Lane 2 TX termination and VOD calibra
    tion OK (500 us)
    altera_adxcvr 10024000.axi-ad9371-tx-xcvr: Lane 3 TX termination and VOD calibra
    tion OK (500 us)
    altera_adxcvr 10024000.axi-ad9371-tx-xcvr: Altera ADXCVR (17.01.a) probed
    altera_adxcvr 10034000.axi-ad9371-rx-xcvr: Lane 0 CDR/CMU PLL & RX offset calibr
    ation OK (400 us)
    altera_adxcvr 10034000.axi-ad9371-rx-xcvr: Lane 1 CDR/CMU PLL & RX offset calibr
    ation OK (500 us)
    altera_adxcvr 10034000.axi-ad9371-rx-xcvr: Altera ADXCVR (17.01.a) probed
    altera_adxcvr 10044000.axi-ad9371-rx-os-xcvr: Lane 0 CDR/CMU PLL & RX offset cal
    ibration OK (400 us)
    altera_adxcvr 10044000.axi-ad9371-rx-os-xcvr: Lane 1 CDR/CMU PLL & RX offset cal
    ibration OK (600 us)
    altera_adxcvr 10044000.axi-ad9371-rx-os-xcvr: Altera ADXCVR (17.01.a) probed
    NET: Registered protocol family 17
    altera_adxcvr 10024000.axi-ad9371-tx-xcvr: Setting link rate to 122880000 (lane
    rate: 4915200)
    altera_adxcvr 10034000.axi-ad9371-rx-xcvr: Setting link rate to 122880000 (lane
    rate: 4915200)
    altera_adxcvr 10044000.axi-ad9371-rx-os-xcvr: Setting link rate to 122880000 (la
    ne rate: 4915200)
    ad9371 spi32766.1: ad9371_probe : enter
    ad9371 spi32766.1: ad9371_probe : enter
    random: crng init done
    ad9371 spi32766.1: framerStatus (0x20)
    ad9371 spi32766.1: ad9371_probe : AD9375 Rev 4, Firmware 5.2.2 API version: 1.5.
    2.3566 successfully initialized
    cf_axi_dds 10054000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.0
    1.b) at 0x10054000 mapped to 0xf0054000, probed DDS AD9371
    cf_axi_adc 10050000.axi-ad9371-rx-hpc: ADI AIM (10.01.b) at 0x10050000 mapped to
     0xf0050000, probed ADC AD9371 as MASTER
    Freeing unused kernel memory: 3156K (c036f000 - c0684000)
    This architecture does not have kernel memory protection.
    axi-jesd204-rx 10040000.axi-jesd204-rx: Lane 0 desynced (17 errors), restarting
    link
    axi-jesd204-rx 10040000.axi-jesd204-rx: Lane 1 desynced (22 errors), restarting
    link
    Starting logging: OK
    Initializing random number generator... done.
    Starting network: OK
    altera_tse 10181000.ethernet eth0: device MAC address b2:94:3d:6e:11:8f
    altera_tse 10181000.ethernet eth0: TSE revision 1201
    altera_tse 10181000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
    Network cable is plugged
    udhcpc: started, v1.25.0
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: no lease, failing
    altera_tse 10181000.ethernet eth0: Link is Down
    udhcpc: started, v1.25.0
    udhcpc: sending discover
    altera_tse 10181000.ethernet eth0: Link is Up - 100Mbps/Half - flow control off
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: no lease, failing
    Starting dropbear sshd: OK
    Starting IIO Server Daemon
    
    Welcome to Buildroot
    buildroot login: root
    Password:
    # ifconfig
    eth0      Link encap:Ethernet  HWaddr B2:94:3D:6E:11:8F
              UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
              RX packets:21 errors:0 dropped:21 overruns:0 frame:0
              TX packets:15 errors:0 dropped:0 overruns:0 carrier:0
              collisions:0 txqueuelen:1000
              RX bytes:4941 (4.8 KiB)  TX bytes:5130 (5.0 KiB)
              Memory:10181000-101813ff
    
    lo        Link encap:Local Loopback
              inet addr:127.0.0.1  Mask:255.0.0.0
              UP LOOPBACK RUNNING  MTU:65536  Metric:1
              RX packets:0 errors:0 dropped:0 overruns:0 frame:0
              TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
              collisions:0 txqueuelen:1
              RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
    
    #

    The driver correctly recognized the AD9375 and Linux was launched.

    However, there was a problem in creating a Linux image (~/nios2/linux/vmlinux).

    The default configuration only wakes up the kernel panic during boot.

    I had to invoke "make menuconfig" and change the path "General setup"-> "Initramfs source file (s)."

    "arch/niso2/boot/rootfs.cpio.gz" -> "arch/niso2/boot/rootfs.cpio.gz/rootfs_nios2.cpio.gz" 

    Then I tried to connect with IIO Oscilloscope, but I could not connect to the network.

    • Connect with PC and P2P
    • Connect to in-house LEN and get address from HDCP server

    I tried two methods, but if I confirm it with ifconfig, it seems that I can not get the address.

    Is it possible to connect to the IIO Oscilloscope with this design?

    If I can connect, what action do I need to do to connect?

    Thanks and Regards,

    Taka

  • Hi Taka,

    The initial commit missed to set mykDevice.tx->txProfile->enableDpdDataPath when AD9375 was detected. Please try again: https://github.com/analogdevicesinc/no-OS/tree/ad9375

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you for your great support !

    When I run the downloaded source, it worked without errors.

    So I have two questions.

    The difference from before is executing mykDevice.tx-> txProfile-> enableDpdDataPath = 1 before calling MYKONOS_initialize ().

    (1) In the AD9375, MYKONOS_initialize () will be called twice. Is there a problem? Is there a problem with processing that calls together only once?
    (2) Is there no problem with setting "1" to enableDpdDataPath as a structure setting? 

    Thanks and Regards,
    Taka
  • MYKONOS_getProductId() can't be run before initializing the chip through MYKONOS_initialize(), so to differentiate between AD9371 and AD9375, the two functions should be called. If AD9375 was detected, enableDpdDataPath member must be enabled, so in order to update this setting, MYKONOS_initialize() will be called again. This is valid for the profiles posted on the GitHub - if someone generates a dedicated AD9375 profile (where enableDpdDataPath is set by default), MYKONOS_initialize() can be called only once.

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you very much for your kindness support.

    I was able to understand.

    Thanks and Regards,
    Taka