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About enabling DPD when using ADRV 9375-W / PCBZ with Intel Arria 10 GX development kit

Hi

We have the design of Intel Arria 10 GX development kit using AD9371.
(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an792.pdf)

I would like to connect to ADRV9375-W / PCBZ using this design and try out the function of DPD.

I changed the source code with reference to the AD9371 Linux Driver and so on.

However, MYKONOS_waitInitCals () caused an error.

(If I do not add "DPD_INIT | CLGC_INIT | VSWR_INIT" to initCalMask, no error will occur.)

Specifically, it is CMB_SPIReadByte (device-> spiSettings, MYKONOS_ADDR_ARM_CMD_STATUS_ 0 + cmdByteIndex, & cmdByte); which is called in MYKONOS_readArmCmdStatusByte(),
This is because 224 is stored in cmdByte.

(It is 0 when it operates normally)

What does this mean?

Major Changed Code ]

< config_AD9371.c >

	uint32_t initCalMask = TX_BB_FILTER | ADC_TUNER | TIA_3DB_CORNER | DC_OFFSET |
	TX_ATTENUATION_DELAY | RX_GAIN_DELAY | FLASH_CAL |
	PATH_DELAY | TX_LO_LEAKAGE_INTERNAL | TX_QEC_INIT |
	LOOPBACK_RX_LO_DELAY | LOOPBACK_RX_RX_QEC_INIT |
	RX_LO_DELAY | RX_QEC_INIT
#ifdef AD9351
	| DPD_INIT | CLGC_INIT | VSWR_INIT ;
#else
	;
#endif

	printf("Mykonos RF Frequency setting Completed\n");
	/*************************************************************************/
	/*****                 Mykonos DPD Initialization                    *****/
	/*************************************************************************/
#ifdef AD9351
	if ((mykError = MYKONOS_configDpd(&mykDevice)) != MYKONOS_ERR_OK)
	{
	    /*** < Info: errorString will contain log error string in order to debug failure > ***/
	    errorString = getMykonosErrorMessage(mykError);
	}

	if ((mykError = MYKONOS_configClgc(&mykDevice)) != MYKONOS_ERR_OK)
	{
	    /*** < Info: errorString will contain log error string in order to debug failure > ***/
	    errorString = getMykonosErrorMessage(mykError);
	}

	if ((mykError = MYKONOS_configVswr(&mykDevice)) != MYKONOS_ERR_OK)
	{
	    /*** < Info: errorString will contain log error string in order to debug failure > ***/
	    errorString = getMykonosErrorMessage(mykError);
	}
	printf("Mykonos DPD Config Completed\n");
#endif
	/*************************************************************************/
	/*****                Mykonos Set GPIOs                              *****/
	/*************************************************************************/

< myk_config.c >

static mykonosTxSettings_t txSettings =
{
    &txProfile,     /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/
    &deframer,      /* Mykonos JESD204b deframer config for the Tx data path*/
    TX1,            /* The desired Tx channels to enable during initialization*/
    0,              /* Internal LO=0, external LO*2 if =1*/
    1000000000U,     /* Tx PLL LO frequency (internal or external LO)*/
    TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
    10000,          /* Initial and current Tx1 Attenuation mdB*/
    10000,          /* Initial and current Tx2 Attenuation mdB*/
    &dpdConfig,     /* <NULL>DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/
    &clgcConfig,    /* <NULL>CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
    &vswrConfig     /* <NULL>VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
};

Thanks and Regards,

Parents Reply Children
  • Hi. Dragos

    Thank you for your support.

    I will answer your question.

    > What did you change in the source code?
    Basically my modified is only the above code.

    1. I added DPD_INIT, CLGC_INIT, VSWR_INIT to initCalMask.
    2. I added MYKONOS_configDpd(), MYKONOS_configClgc() and MYKONOS_configVswr() call after MYKONOS_setRfPllFrequency().
    3. I modified mykonosDpdConfig_t, mykonosClgcConfig_t, mykonosVswrConfig_t which is a member of static mykonosTxSettings_t txSettings from NULL to a pointer.

    Other than that, "Mykonos API version" has been replaced from "1.2.05.3518" to "1.5.2.3566".
    (In addition, Mykonos M3.bin has also been replaced.)

    > The Linux driver should support ADRV9375 without any change.
    I do not use Linux in my evaluation environment.
    It is a no-OS environment using Nios II.
    The reason for writing "source code with reference to the AD9371 Linux Driver" in the above description is because we could not find the code using DPD with no-OS.
    Thanks and Regards,
    Taka
  • Ok, I will move the thread to the corresponding place.

    Thanks,
    Dragos

  • We will add these days Altera support to https://github.com/analogdevicesinc/no-OS/tree/master/projects/ad9371/src (everything needed for the project - API, firmware - is included) - it would be better to start from this no-OS version instead of the original one (https://github.com/analogdevicesinc/no-OS/tree/master/ad9371/sw).

    We will let you know when it's be ready.

    Thanks,
    Dragos

  • The described changes were added: https://github.com/analogdevicesinc/no-OS/tree/ad9371_altera - they will be merged on master soon.

    Ca you do a test using this version?

    We'll try to also add support for ADRV9375.

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you for your support.

    I checked the downloaded source code.

    As a result, I couldn't get it to work well.

    So I have four questions.

    (1) Is the FPGA design correct at github.com/.../a10gx ?

    (2) I added files in the following folder to the Nios II Project. Is this correct?

    github.com/.../src
    github.com/.../drivers

    (3) In Nios II BSP-Editor's Linker Script, everything except .entry is DDR3. Do you need to change it?

    (4) It seems that processing related to DPD is not implemented in the source code, but specifically where does DPD related processing exist?

    Thanks and Regards,
    Taka
  • Hi,

    1. https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9371x/a10gx - this is the right project - make sure to disable the MMU for the no-OS setup - https://wiki.analog.com/resources/fpga/docs/build#alterabuild_your_desired_project

    2. You need the files specified in the README file.

    3. No changes are required to the default linker script.

    4. We merged the previous changes to master. The AD9375 ones are located on a dedicated branch: https://github.com/analogdevicesinc/no-OS/tree/ad9375/projects/ad9371/src

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you for your support.

    And I am sorry again and again.

    I tested the downloaded source code.

    As a result, I couldn't get it to work well.

    I will show you my evaluation environment.

    (Q1) I'm connecting like this, is there any problem?

    I operated as follows.

    (1) I added the file described in the README to the newly created Nios II project and executed it.

    Nios II Console Output Results ]

    Please wait...
    WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.
    rx_device_clk_pll: FPLL PLL calibration OK (1200 us)
    tx_device_clk_pll: FPLL PLL calibration OK (1000 us)
    rx_os_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    tx_adxcvr: ATX PLL calibration OK (20 ms)
    tx_adxcvr: Lane 0 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 1 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 2 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 3 TX termination and VOD calibration OK (600 us)
    rx_os_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_os_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    device->tx->dpdConfig structure has NULL pointer in MYKONOS_configDpd()

    (Q2) It was output as "WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.". Is there a problem?

    (2) Because "device->tx->dpdConfig structure has NULL pointer in MYKONOS_configDpd()" was output, in myk.c
    changed mykonosDpdConfig_t, mykonosClgcConfig_t, and mykonosVswrConfig_t from NULL to a structure pointer.

    static mykonosTxSettings_t txSettings =
    {
        &txProfile,     /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/
        &deframer,      /* Mykonos JESD204b deframer config for the Tx data path*/
        TX1_TX2,        /* The desired Tx channels to enable during initialization*/
        0,              /* Internal LO=0, external LO*2 if =1*/
        2500000000U,    /* Tx PLL LO frequency (internal or external LO)*/
        TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
        10000,          /* Initial and current Tx1 Attenuation mdB*/
        10000,          /* Initial and current Tx2 Attenuation mdB*/
        &dpdConfig,           /* DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/
        &clgcConfig,           /* CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
        &vswrConfig            /* VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
    };

    (3) I tried to run again.

    [ Nios II Console Output Results ]

    Please wait...
    WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.
    rx_device_clk_pll: FPLL PLL calibration OK (800 us)
    tx_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_os_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    tx_adxcvr: ATX PLL calibration OK (20 ms)
    tx_adxcvr: Lane 0 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 1 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 2 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 3 TX termination and VOD calibration OK (600 us)
    rx_os_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_os_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Unknown error was encountered.

    It seems that an error occurred in MYKONOS_waitInitCals ().
    The return value was MYKONOS_ERR_WAIT_INITCALS_CALFAILED.

    (Q3) What kind of problems can be considered as the cause of not working properly?

    Thanks and Regards,
    Taka

  • Hi,

    The  AD9528_initialize() warning can be caused by an improper/nonexistent clock connected to REF_CLK_IN (in our reference design, a clock of 30.72 MHz needs to be provided).

    Your changes to the txSettings are correct.

    By the way, can you also do a test by treating your AD9375 as a AD9371 (set prodid to AD9371_PRODID)?

    Thanks,
    Dragos

  • Hi. Dragos

    Thank you for your answer.

    > in our reference design, a clock of 30.72 MHz needs to be provided.

    Thank you for your advice.

    The input frequency has been changed to 30.72 MHz.

    WARNING has disappeared, but the error in MYKONOS_waitInitCals () has not changed as before.

    > By the way, can you also do a test by treating your AD9375 as a AD9371 (set prodid to AD9371_PRODID)?

    I changed line 71 of headless.c and made it work.

    //#define AD9371_PRODID		0x03
    #define AD9371_PRODID		0x06
    #define IS_AD9371(prodid)	(prodid == AD9371_PRODID)

    When operating as an AD9371, no errors appear to occur.

    [ Nios II Console Output Results ]

    Please wait...
    rx_device_clk_pll: FPLL PLL calibration OK (1000 us)
    tx_device_clk_pll: FPLL PLL calibration OK (1000 us)
    rx_os_device_clk_pll: FPLL PLL calibration OK (1200 us)
    rx_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    tx_adxcvr: ATX PLL calibration OK (20 ms)
    tx_adxcvr: Lane 0 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 1 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 2 TX termination and VOD calibration OK (600 us)
    tx_adxcvr: Lane 3 TX termination and VOD calibration OK (600 us)
    rx_os_adxcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
    rx_os_adxcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Calibrations completed successfully
    rx_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.881 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_jesd lane 0 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
    	K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x47, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    rx_jesd lane 1 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
    	K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x48, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    tx_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.881 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	SYNC~: deasserted
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd status:
    	Link is enabled
    	Measured Link Clock: 122.881 MHz
    	Reported Link Clock: 122.880 MHz
    	Lane rate: 4915.200 MHz
    	Lane rate / 40: 122.880 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_os_jesd lane 0 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 51 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
    	K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x43, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    rx_os_jesd lane 1 status:
    Errors: 0
    	CGS state: DATA
    	Initial Frame Synchronization: Yes
    	Lane Latency: 1 Multi-frames and 49 Octets
    	Initial Lane Alignment Sequence: Yes
    	DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
    	K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
    	FCHK: 0x44, CF: 0
    	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    	FC: 4915200 kHz
    tx_dac: Successfully initialized (245761108 Hz)
    rx_adc: Successfully initialized (122880554 Hz)
    Done

    Are there any other possible causes?

    Thanks and Regards,
    Taka

  • Hi Taka,

    This is good.

    I've added a small change to the ad9375 branch (https://github.com/analogdevicesinc/no-OS/tree/ad9375/projects/ad9371/src) - call MYKONOS_radioOff() before configuring DPD, CLGC andVSWR. However, I'm not sure if it helps since my assumption is that the Radio is anyway OFF at that moment. Unfortunately, I wasn't able to test this - I'm waiting for a ADRV9375 board.

    You can also have a look at our Linux driver (https://github.com/analogdevicesinc/no-OS/commit/455a34c91020241bb65149b4734c11ef835a5b8c) - the AD9375 driver support was tested over there.
    We also have an ADRV9371 device tree for Arria 10 GX - the only required change if ADRV9375 is used would to update the compatible string (compatible = "ad9375" instead of compatible = "ad9371") - https://github.com/analogdevicesinc/linux/blob/altera_4.9/arch/nios2/boot/dts/a10gx_adrv9371.dts#L285
    If you want to give it a try, we can give some instructions.

    Thanks,
    Dragos