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Digital Loopback Issues in Ad9361 Custom board


We have a custom AD9361 board using Zynq and No-Os software from ADI. Everything is working fine in this board, including the Rx and Tx tuning (in fact this board is in production). But when we enable digital loopback, we see that the digital loopback actually sends a pattern data on Rx, instead of looping back Tx data to Rx. We have tried sending constants on Tx path, including all 0s and all 1s, but we still see this pattern (see figure below). We are enabling register 0x3f5 (D0) bit right after "AD9361 successfully configured" message is displayed. 

My questions are:

1) Are we doing anything wrong ?

2) Why does digital loopback not work even though the board is working good in all normal operations ?

3) However, when we enable BIST by setting (0x3F4 = 0x5B), we see a sinusoidal signal though. Why only BIST is working but not loopback ?

PS : We are testing digital loopback on this board which is working good because we to use the same firmware on a newer version board wherein the Rx and Tx tuning are both failing.




  • Hi,

    There is a dedicated function that can be used for enabling the supported loopbacks:

    - Digital TX → Digital RX loopback : The loopback happens inside the AD9361/4 close to the internal digital interface block. The entire RF section is bypassed. This can be used to validate (monitor on RX) the digital samples/symbols sent to the device.

    - RF RX → RF TX loopback : The loopback happens in the ADI's provided HDL core. The Transmitter will transmit anything that the receiver receives. The entire RF chain is active (Sample rates, RF bandwidth and FIR settings will all effect the transmission).

    Can you use ad9361_bist_loopback() function for enabling the desired option (mode 0 - loopback is disabled; mode 1 - loopback (AD9361 internal) TX->RX; mode 2 - loopback (FPGA internal) RX->TX) instead of directly writing to SPI registers?



  • Hi Dragos,

    Thanks for your support !

    I used the following ad9361_bist_loopback(phy, 1); to enable Digital loopback of AD9361. However, I still see the similar pattern like before(See attached figure containing both hex and analog plots). Any idea why we are seeing this ?

    FYI, we are driving the dac_data(63:0) and dac_valid_0/1/2/3 directly from our hdl code. 



  • I figured out what the problem was : Since we were driving the dac data, we had to enable the source of dac as dma..So, after executing dac_init(ad9361_phy, DATA_SEL_DMA, 1); I am able to see the digital loopback work correctly now.

    Thanks for your support !

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