coustom data on AD9361 driver no_os not working

I am using zc702 with xilinx vivado platform to configure the ad9361 based FMCOMMS3 FMC.

when i am using the driver in the default state ,that is with function "dac_init(ad9361_phy, DATA_SEL_DDS, 1)" then i am able to get a sine wave with the set tone from the internal dds.

But when i disable the internal DDS using "DDS_Disable = 1 " on the axi_ad9361 ip, and then configuring the no_OS driver to DATA_SEL_DMA mode using the function "dac_init(ad9361_phy, DATA_SEL_DMA, 0)" I get no output the differential ports.

Can some one please explain why this is not working and let me know if i am missing any step.

FYI: I have removed the DAC_DMA and used and custom RTL logic to continuously send data to the axi_ad9361 ip.   

Thanks in advance.

Parents
  • 0
    •  Analog Employees 
    on Jan 28, 2019 4:20 PM over 1 year ago

    Hi,

    Are you generating 64-bit data for the 2 channels (I and Q pairs)?
    Is your logic sending data at the rate that the axi_ad9361 requests it? (enable, valid and data signals). Can you check this signals with and ILA?
    https://wiki.analog.com/resources/fpga/docs/axi_ad9361

    What do you get on the output of the fmcomms3? Can your logic transmit a simple sinewave? To validate the data path.
    What do you get on the UART console?

    Andrei

  • hi andrei_g ,

    I Thank you for the reply,

    I wish to generate 16 bit each (I and Q pairs) right from the PL rather than from the PS.

    hence i would like to know what are the changes to be made on the no_OS driver apart from configuring the dac registers from the given function "dac_init(ad9361_phy, DATA_SEL_DMA, 0)" . Provided that i am sending a continuous stream of data on the dac_data ports using the an RTL logic.(The RTL logic for the source of stream data is probed and tested and is giving a proper stream of data)

    The problem I am facing is the dac_enables on the axi_ad9361 ip are not going high even though i have configured the TX data_select to DMA mode though the dac_init function.Hence my doubt is if i have forgot some registers to activate on the AXI_AD9361 ip.

    for your reference I have attached a screen shot of the hardware design.

Reply
  • hi andrei_g ,

    I Thank you for the reply,

    I wish to generate 16 bit each (I and Q pairs) right from the PL rather than from the PS.

    hence i would like to know what are the changes to be made on the no_OS driver apart from configuring the dac registers from the given function "dac_init(ad9361_phy, DATA_SEL_DMA, 0)" . Provided that i am sending a continuous stream of data on the dac_data ports using the an RTL logic.(The RTL logic for the source of stream data is probed and tested and is giving a proper stream of data)

    The problem I am facing is the dac_enables on the axi_ad9361 ip are not going high even though i have configured the TX data_select to DMA mode though the dac_init function.Hence my doubt is if i have forgot some registers to activate on the AXI_AD9361 ip.

    for your reference I have attached a screen shot of the hardware design.

Children
  • +1
    •  Analog Employees 
    on Jan 29, 2019 9:38 AM over 1 year ago in reply to @nithinvarma

    Hi,

    I took a closer look... a few reasons why it will not work by directly using
    "dac_init(ad9361_phy, DATA_SEL_DMA, 0)"

    1), dac_init(ad9361_phy, DATA_SEL_DMA, 0), does nothing, this is used in the case of fmcomms5 programing the phy, not the DMA or DMA source for axi_ad9361; fmcomms5 has two AD9361, different system.
    2). You removed the DMA from the system... by using that function the software will hang trying to configure the missing DMA. You will have to only change the data source using dac_datasel(), use -1 to select all channels at once.

    I'm one of the HDL folks, so about your design.
    - Not sure on which clock are you generating data, (it should be on l_clk).

    - You are using un channel on the AD9361 (not connecting the second I/Q pair), If you intend to use only one channel you can set the device in 1R1T mode, but then you will have to connect the valid signal to your logic... hence the valid will not be always high.

    - AD9361 is a 12-bit device (on the Tx side only the first 12 are used from the given 16, the Rx is different the data is on the last 12 bits the first 4 are sign extension).

    You might find this usefull https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt


    The UART messages are really important.Slight smileSlight smile
    I embedded a lot of links through the text above make sure you can see them.

    Andrei

  • Thanks Andrei,

    I have missed the valid logic of the axi_ad9361 ip. adding that to the design solved my problem.