i'm having an calibration timeout error of (0x244, 0x80) with AD9361.
i'm using the Tiva TM4CNCPDT1294 controller to generate the communication with the AD9361.
the configuration file that is being used is for 947.5 MHz.
Please Help.
AD9361
Recommended for New Designs
The AD9361 is a high performance, highly integrated radio
frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and
4G base station applications....
Datasheet
AD9361 on Analog.com
i'm having an calibration timeout error of (0x244, 0x80) with AD9361.
i'm using the Tiva TM4CNCPDT1294 controller to generate the communication with the AD9361.
the configuration file that is being used is for 947.5 MHz.
Please Help.
Can you please check the synthesizer power supply voltage level and ref clock signal quality?
Which software driver you are using, Linux or No-OS?
i have already verified the synthesizer power supply voltage level and ref clock signal quality and i'm using no OS
What is the reference clock that you are using.?
Hope you are updating the SW accordingly AD9361_InitParam->reference_clk_rate .
30720000UL, //reference_clk_rate
this is the clock rate that i'm using
Moving this post to NO-OS forum for more comments on SW .
Can you describe you clocking hardware setup? What reference clock do you use? What amplitude has you signal?
Dragos
i'm using a clock buffer K00101 giving a frequency of 30.72 MHz through a crystal.
amplitude of 2.5 v
Did you set xo_disable_use_ext_refclk_enable ?
0,//xo_disable_use_ext_refclk_enable
no this is set to disable