Reducing the 1 uF bypass capacitor on the B channel and the 10uF bypass capacitor on the A channel, which is powered from the internal Viso dc to dc converter, will increase the supply voltage ripple and the output voltage ripple, which at some point will effect the performance of the circuit and will not reduce the average current draw on the Viso supply, or the VDD1 primary supply current. If you intend to reduce the VDD1 supply current, this can be done by adjusting the voltage at the Vadj pin which will reduce the duty cycle of the internal dc to dc converter. Depending on the output current needed, figure 13 of the datasheet shows how you can select the PWM duty factor of the internal dc to dc converter, where a lower duty cycle will reduce the VDD1 supply current. Figure 14 then shows the upper/lower Vadj divider resistors to use for the chosen PWM duty factor.
Alternatively, you can just adjust the resistor values until you get the supply current reduction needed. You need to be careful not to reduce the duty factor too much or the output voltage will drop too much and you will not have a reliable voltage to drive the gate.