Thanks for raising this up. We are aware of some similar issues and I believe our internal team is working on it.
As per my understanding of SPORT module pins:
- When SPORT is operating in internal clock mode (ICLK=1) then we cannot use SPORT_CLK pin in GPIO/other function mode. The corresponding pin must be configured as SPORT_CLK pin. (If we use SPORT_CLK pin as GPIO, signal on SPORT Data pin gates according to status of that GPIO pin)
- There is no such limitation on SPORT_FS pin, when SPORT is operating in internal FS mode (IFS=1).
- As Primary Transmit Data pin is enabled by default (with TSPEN bit is set), we must configure DTPRI Data pin in PORT mux.
- Secondary Data pin can be disabled in PORT Mux.
This is what my understanding is. If you can contact to private support channel, I will confirm these from our internal team.
But by looking at your description, I think you are facing some problems with SPORT_FS and SPORT_DRPRI pins as well (which I think, should not). If you can provide more information about these problem, then that would be helpful.