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TDM4 pulse mode ADAU1361 issues

Question asked by coco86 on Sep 8, 2017
Latest reply on Sep 26, 2017 by coco86

Hello all !

 

I am trying to get the ADAU 1361 working in TDM4 pulse mode (128 bits) but I encounter some issues with this configuration.

 

1st issue:

When I configure the codec with frames beggining on the falling edge of the pulse, i mesure that it starts on rising edge. When I configure a frame start on the rising edge, then the codec stops to output any data on its slots (active slots are slots 0 and 2, slot 1 and 3 are unused).

 

When I want to work in this configuration (frame start on rising edge, 1 BCLK delay) everything is all right, except that I have to configure "frame starts on falling edge" to get it starting on rising edge which is kind of confusing...

 

2nd issue:

In a second case, i want the codec to have a data bit clock delay equals to 8 BCLK. I then shift my data so they arrive shifted to the codec by 8BCLK. Besides, data i send to the DAC are exactly synchronous with data sended by the codec (DAC and ADC frames start at exactly the same time, so the shift seems to be OK). Nonetheless, the DAC seems to misunderstood what it receives. As a result i have no audio analog signal outputted. This is also confusing because in the case where data are left justified (frame begins on rising edge, 1BCLK delay), when i send a 24bits audio signal (a 440Hz sinewave fullscale for information) i got exactly what is expected on outputs, and sound is properly heard on loudspeaker.

 

Does these issues correspond to some known problems ?

Is TDM4 mode with pulse mode had been qualified for all BCLK and LRCLK polarity ?

 

see under, my full ADAU1361 configuration :

 

    /*0x4000*/  { ADAU1361_CLKCTRL,             0x00 },    /*Reset CLK CONTROL                          */

    /*---------------------------------------------PLL--------------------------------------------------*/

    /*0x4002*/  { ADAU1361_PLLCTRL1,            0x00 },    /*PLL CONTROL REG 1 MCLK = 24MHz, fs = 48KHz */

    /*0x4003*/  { ADAU1361_PLLCTRL2,            0x7D },    /*PLL CONTROL REG 2 MCLK = 24MHz, fs = 48KHz */

    /*0x4004*/  { ADAU1361_PLLCTRL3,            0x00 },    /*PLL CONTROL REG 3 MCLK = 24MHz, fs = 48KHz */

    /*0x4005*/  { ADAU1361_PLLCTRL4,            0x0C },    /*PLL CONTROL REG 4 MCLK = 24MHz, fs = 48KHz */

    /*0x4006*/  { ADAU1361_PLLCTRL5,            0x23 },    /*PLL CONTROL REG 5 MCLK = 24MHz, fs = 48KHz */

    /*0x4007*/  { ADAU1361_PLLCTRL6,            0x01 },    /*PLL CONTROL REG 6 MCLK = 24MHz, fs = 48KHz */

    /*--------------------------------------------CLOCK-------------------------------------------------*/

    /*0x4000*/  { ADAU1361_CLKCTRL,             0x01 },    /*Enable Clock after setting the PLL         */

 

    /*-----------------------------------MIC_INT => LEFT ADC--------------------------------------------*/

    /*0x400E*/  { ADAU1361_RECVLCL,             0xE3 },   /* LDVOL = 30db                               */

    /*0x400B*/  { ADAU1361_RECMLC1,             0x08 },   /* LDBOOST = Odb                              */

    /*0x400A*/  { ADAU1361_RECMLC0,             0x01 },   /* MX1EN = 1                                  */

    /*-----------------------------------RIGHT DAC => HP_INT--------------------------------------------*/

    /*0x401C*/  { ADAU1361_PLBMLC0,             0x41 },   /* MX3EN = 1 - MX3RM = UNMUTE                 */

    /*0x401D*/  { ADAU1361_PLBMLC1,             0x00 },   /* TODO: MX3G1 to 0dB for test                */

    /*0x4020*/  { ADAU1361_PLBMLLO,              0x03 },   /* MX5EN = 1 - MX5G3 = 0db                    */

    /*0x4025*/  { ADAU1361_PLBLOVL,              0xE6 },   /* set LOUT volume to 0dB                     */

    /*0x4029*/  { ADAU1361_PLBPWRM,             0x03 },   /* Playback Right anf left channel EN         */

 

    /*-----------------------------------MIC_EXT => RIGHT ADC-------------------------------------------*/

    /*0x400F*/  { ADAU1361_RECVLCR,             0xFF },   /* RDVOL = 0db                                */

    /*0x400D*/  { ADAU1361_RECMRC1,             0x08 },   /* RDBOOST = Odb                              */

    /*0x400C*/  { ADAU1361_RECMRC0,             0x01 },   /* MX2EN = 1                                  */

    /*------------------------------------RIGHT DAC => HP_EXT-------------------------------------------*/

    /*0x401E*/  { ADAU1361_PLBMRC0,             0x41 },   /* MX4EN = 1 - MX4RM = UNMUTE                 */

    /*0x4021*/  { ADAU1361_PLBMRLO,             0x09 },   /* MX6EN = 1 - MX6G4 = 0db                    */

    /*0x4026*/  { ADAU1361_PLBLOVR,             0xE6 },   /* set ROUT volume to 0dB                     */

    /*--------------------------------------RETOUR D'ECOUTE---------------------------------------------*/

    /*0x401F*/  { ADAU1361_PLBMRC1,             0x00 },   /* MX4G2 = -12dB                              */

 

    /*0x4015*/  { ADAU1361_SPRTCT0,             0x32 },   /*TDM4 mode                                   */

    /*0x4016*/  { ADAU1361_SPRTCT1,             0x62 },

    /*0x4017*/  { ADAU1361_CONVCT0,             0x00 },

    /*0x4018*/  { ADAU1361_CONVCT1,             0x00 },   /*TODO : to be continued...                   */

    /*0x4019*/  { ADAU1361_ADCCTL0,             0x03 },   /*ADC left and right ON                       */

    /*0x402A*/  { ADAU1361_DACCTL0,             0x03 },   /*TODO : to be continued...                   */

 

Thank you in advance.

 

Corentin.

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