I have an inherited design with an ADUM5412 Quad Channel Isolator that is experiencing failures. The failure mode is the VDD2 end up shorted to GNDiso. The failures occurs over a period of operational time, not immediately. In reviewing the design I see that the designer has tied Viso and Vsel directly to GNDiso and PDIS to 3.3V. I am wondering if having Viso and Vsel tied directly to GNDiso could be causing a chip failure. All the example schematic I have seen show some resistive load between Vsio and GNDiso. Does anyone know if tieing them directly could cause a failure over time?