CMOS output drivers work very well for lower sample rate ADCs up to approximately 200 MSPS. As the speeds increase with CMOS output drivers, the power consumption also increase. Typically each output data bit requires a CMOS output. As the resolution and speeds of ADCs increase, the power consumption becomes an issue and this technology is no longer desirable to use.
LVDS output drivers are typically employed on ADCs with sample rates from approximately 80 MSPS up to around 500 MSPS when using DDR (double data rate) where two data bits are output for every period of the sample clock. The output format is mixed parallel-serial where two data bits are output on each LVDS pair and the total number of data outputs is approximately half the resolution of the converter.This type of driver can be used reilably up to around 600 MSPS with DDR and up to 1200 MSPS SDR (single data rate). The driving factor is the upper data rate limit of approximately 1.2 Gbps that can be supported using LVDS.
CML is emerging in data transfer standards like JESD204 where data rates are used up to 3.125 Gbps currently and are looking to push 6-10 Gbps. Where the LVDS output drivers are used in a mixed parallel-serial interface in the ADCs that ADI offers, CML drivers are employed in the complex serial interface defined by the JESD204 standard. In this case, there is typically one serial lane (or data output pair) per ADC, so one of the benefits is that the number of I/O required is greatly reduced.