8 Replies Latest reply: Mar 11, 2011 10:12 AM by abdolyab RSS

    Programmer un AD9954 par fpga




      J'utilise un dds pour générer une fréquence de 126MHz. J'ai un quartz 20MHz et je veux multiplier cette fréquence par 20 pour obtenir une horloge interne de 400MHz. Pour ce faire j'envoie à mon dds le mot suivant : x"010000A4" dont le premier octet constitue l'insruction pour écrire au registre cfr2. Ensuite j'envoie le mot x"0050A3D70A" dont le premier octet constitue l'insruction pour écrire au registre FTW et les quatre suivants le tunning word correspondant à 126 MHz. A la fin de l'envoi je met io_update à 1 pour la mise à jour des régistres. Etant donnée que mon fpga tourne à 12,5MHz j'ai mis la même comme horloge de travail du dds.

      Mon problème est qu'à la sortie j'obtiens un signal trop bruité et pas à la fréquence que je souhaite avoir. 


      1) Pourriez vous me dire si ma manière d'envoyer les données est correcte?




        • 1. Re: Programmer un AD9954 par fpga

          Hello Abdolyab-


          Thanks for using EngineerZone.  As stated in our community Code of Conduct (Analog Devices EngineerZone Code of Conduct) we are only able to support English language posts on EngineerZone.  Sorry for the inconvenience.




          EngineerZone Community Manager

          • 2. Re: Programmer un AD9954 par fpga

            Sorry! I will try to answer my question in english.


            I'm using an ad9954 to generate a sine at 126 MHz. In my code written in vhdl I send two block of data. The first one is x"010000A4" for writting in the cfr2 register a factor of the internal multiplier ( I use a quartz of 20 MHz so to have 400MHz for the internal clock I use a factor equal 20). The second block is x"0050A3D70A" to write in the FTW the frequence tunning word corresponding to 126MHz. After that I set the io_update pin for updating. The matter is I don't see any sigal at the dds's output. Do you thing I forget something in my programme? How can I know if my programme is receive by the dds?



            • 3. Re: Programmer un AD9954 par fpga

              Hi Abdolyab,

              Your first block looks good. It's programming the PLL multiplication to 20x.

              The second block looks good, less the address. I assume the second block is programming

              address 04h, not 00h per below. If so, that should work after the IO_UPDATE.


              If not, check the following.


              1) Make sure to send a master reset after power up to place the device in a known state. It also initializes the SPI port.


              2) Check the SYNC CLK pin. If the SYNC CLK should be running at 1/4th the internal system clock rate. In this case, 100MHz. You could send the IO_UPDATE after the first block and then check the SYNC_CLK pin. There's no reason to go farther until that is occurring. If not, you could send your schematic to look over.

              • 4. Re: Programmer un AD9954 par fpga

                Hi DSB,


                Thanks for your response!


                I have send that block x"000000A4" indor to check if my sync_clk is running at 1/4th of sys_clk, in my case 400MHz. But in the the sync_clk output pin I always  have 5MHz, that means the multiplication per 20 is not done by the dds module and so data are not accepted. Before sending the block I set the reset pin and after setting the io_update pin  I clear it. But nothing change. In the device I have several supplies but I don't connect all, I just supply separatly one AVDD, one DVDD, the DVDD_IO and the ground corresponding to them. So I thing my device is well supplied and don't understand why it doesn't accept data from the fpga. Do you have any idea please?



                • 5. Re: Programmer un AD9954 par fpga

                  Hi Abdolyab,

                  Can you please send your schematic showing all AD9954 pin connections? Or, tell how each pin is configured. I want to rule out a pin connection issue. Having one AVDD, DVDD, DVDD_IO is fine.

                  • 6. Re: Programmer un AD9954 par fpga

                    You can see in the attached file the pins connection.



                    • 7. Re: Programmer un AD9954 par fpga

                      Hi Abdolyab,

                      Per the attachment, it appears there's many pins unconnected. As far as the power supply pins, I thought all AVDD pins were tied together but going to one supply. The same for DVDD. You cannot leave these power supply pins unpowered including ground pins because inside the IC power on one pin is not common to all the circuits.


                      Next, there's many CMOS input pins floating.

                      These pins need to be driven too.


                      Ground or set to logic 0 the following CMOS logic inputs, if not used

                      Pins 35,37,39,47,48.

                      Also pin 12 must have the external loop filter populated see figure table 4 in the data sheet for valuses and the AD9954 evaluation board schematic connection.

                      Also, the unused DAC output needs to terminated regardless.

                      • 8. Re: Programmer un AD9954 par fpga

                        Hello DSB,


                        Thank you for you interesting comments, I change my schematic following your advices. Unfortunatly nothing changes and I assume that my device was detroyed because of my first mistakes (I though that all supplies were tied internally) and I'm thinking to replace it by another device. I'll tell you if things go well.


                        Have a good week-end