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ADIsimCLK and zero delay errors

Question asked by gbredthauer on Feb 4, 2015
Latest reply on Feb 10, 2015 by gbredthauer

I'm using an AD9522-3.  The reference clock is 100 MHz.  The VCO will operate at 2000 MHz.  OUT0 will run at 100 MHz, and be fed back to the AD9522 for zero delay alignment.

 

In ADIsimCLK, I select the AD9522-3 and then check "Use Zero Delay".  I select OUT0 for feedback, a VCO divider of 2, and an Arm divider of 10.  I enter a PLL/VCO frequency of 2.00 GHz, and a Phase Detector Frequency of 100.0 MHz.  When I click "Next", ADIsimCLK pops up an "Error" window saying that the AD9522-3 is incompatible with these frequencies, and that no valid prescaler option could be found.

 

I believe this is happening because ADIsimCLK is assuming that the VCO is being fed to the prescaler/N divider instead of CLK0.  For my case, where the reference clock is equal to the feedback clock, I think the R and N dividers should both be set to 1, and 100 MHz is within spec for both the PFD and the prescaler.  Can anyone confirm this bug or suggest a fix/workaround?

 

Thanks,

 

-Greg

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