Q
we have problems during production with your parts - they fail on the PCB and
during income inspection.
A
The most common process oversights associated with their assembly are:
Moisture ingression prior to solder reflow.. The ADIS16265 are classified as
MSL5, per JEDEC J-STD-033. The ADIS16265BCCZ are stored and shipped in
JEDEC-compliant trays, which are vacuum-sealed with moisture absorbing
materials, inside of an anti-static bag. J-STD-033 describes the floor life
(time between bag opening and solder reflow), environment (temperature,
humidity) and pre-reflow bake requirements. If these parameters are not
well-controlled, baking these devices for 24-48 hours at +125°C, inside of a
dry oven (nitrogen), will help remove any residual moisture and reduce its
impact on assembly yields. J-STD-033 is availalbe for download at
http://www.jedec.org/standards-documents.
Solder-reflow time/temperture profile. The ADIS16265 has been qualified to
support the Pb-free solder reflow profile in J-STD-020. Prior to running parts
through an oven, use an accurate thermocouple, placed at the DUT on the PCB, to
verify compliance with the reflow profile in J-STD-020. J-STD-020 is available
for download at: http://www.jedec.org/standards-documents.
Peeling stress can cause the ADIS16265 leads to fracture. This is a common
sensitivity for LGA and BGA packages. A common cause of peeling stress is PCB
separation techniques, which causes the PCB to bend and places the lead
interfaces in "tension." In producing the ADIS16265/PCBZ breakout boards, the
individual PCBs are cut out of the array using a rotating bit, while the PCB
material is clamped. This process has produce more than 1000 boards, with zero
yield loss due to lead fracture. PCB mounting hole location, thickness, width,
length and material rigidity; along with the ADIS16265's proximity to natural
bend points, can impact exposure to peeling stress. Another common technique
for managing peeling stress is the use of an underfill compound, which help
distribute peeling stress across the entire bottom of the package. The
following materials, provided by Hysol, have been used with success: FP4470,
FP4545FC, FC4502, and FP4548. The following tips may help in developing an
under-fill process:
Pre-heat the PCB to +90°C, to help the material whick under the ADIS16265's
package bottom.
Deposit under-fill material on two adjacent edges of the ADIS16265 and allow
the material to wick under the package, for approximately 30 minutes
Bake at +125°C for 30 minutes to help the material set
Bake at +160°C for 90 minutes to fully cure the material