ADIS16488 directly, using provided SPI interface on the connector. So, I'd
like to know if ~CS signal is set up as common open-drain GPIO or not.
The short answers is yes, the ~CS line is in a three state mode when it is not
in use but the processor on the EVAL-ADIS is not +5V tolerant. So, the max
voltages are typically ~3.6V for these lines, even when the processor is not in
use. We have seen a couple of cases where users tried this and appear to
have introduced damaging signal levels (accidentally), so we tend to encourage
the use of the breakout board for this purpose (interface board that comes with
the ADIS16488/PCBZ, for example), rather than the EVAL-ADIS.
NOTE: J1 on the EVAL-ADIS was intended to support connection to products that
use a breakout board (ADIS16228/PCBZ or ADIS16265/PCBZ, for example).