The ADIS16460's data ready signal provides a pulse, every time that new data loads into its output data registers. By changing states while the actual register update is happening, the data-ready provides an effective indicator for the "do not read time." Therefore, triggering on the second edge of the pulse assures avoidance of data collision and minimizes latency. During start-up, while the internal processor is initializing itself for sensor data sampling and processing, the data-ready will go through two non-operational states: an intermediate level, followed by a zero level. After the initialization process completes, the data-ready signal will start pulsing once data production begins. The following picture illustrates this process, where normal pulsing starts ~265ms after application of +3.3V on VDD.
The following picture provides a zoomed view of the time that the data ready stars pulsing, when the ADIS16460's configuration uses the internal sample clock and no decimation (nominal = 2048SPS).
