The MAX30003 is a single channel ECG device but it may be doubled up to produce a dual channel ECG at lower cost than the current competition solutions. The following is an application circuit to achieve 4-Lead (2 Channel) ECG solution with two MAX30003 ICs
To synchronize multiple MAX30001/3s, the hardware requirements are:
- All FCLK pins must be connected to the same clock source.
- The host controller must be able to perform a simultaneous SPI write by asserting all CS pins at the same time.
The synchronization procedure is as follows:
- Set up each device to use the same ECG sample rate (via FMSTR and RATE) and the same digital filter settings and enable ECG via EN_ECG.
- Poll the STATUS register on each device until PLLINT = 0 on all devices (this indicates that the PLL is locked).
- Perform a simultaneous SPI write to all devices: write 0x000000 to SYNCH(0x09).
- On the next FMSTR clock edge following the last (32nd) SCLK rising edge of the SYNCH command, all FIFOs are cleared, and all ECG channels are reset and begin sampling.
- The ECG channels are now synchronized as long as all PLLs remain locked (PLLINT = 0). Monitor the PLLINT status bits to ensure synchronization. If any PLL unlocks, restart the synch procedure.
The time variation between the MAX30003s will be zero since they are all controlled by the same clock source. The latency from the SYNCH command to the first sample appearing in the FIFO depends on the FMSTR setting, the sample rate, and the digital filter settings according to the table below (Also found on page 19 of the datasheet).