ADXL375 watermark interrupt appears before as expected

Hi,

I've configured the ADXL375 in a custom board as follows:

ADXL375_SetRegisterValue(ADXL375_DATA_FORMAT, 0x0B); // right justified (LSB) mode
ADXL375_SetRegisterValue(ADXL375_BW_RATE, 0x0F);     // 3200Hz
ADXL375_SetRegisterValue(ADXL375_THRESH_SHOCK, 0x26);
ADXL375_SetRegisterValue(ADXL375_DUR, 0x50);         //
ADXL375_SetRegisterValue(ADXL375_LATENT, 0x20);      //
ADXL375_SetRegisterValue(ADXL375_WINDOW, 0xF0);      //
ADXL375_SetRegisterValue(ADXL375_SHOCK_AXES, 0x04);  // [X]
ADXL375_SetRegisterValue(ADXL375_INT_ENABLE, 0x02);  // INT1 enable [WATERMARK]
ADXL375_SetRegisterValue(ADXL375_INT_MAP, 0x00);     // INT1 enable map [WATERMARK]    -> [INT1]
// 0b11xxxxxx: FIFO buffer holds the last samples before the trigger event and continues to collect data until full. New data is collected only when the buffer is not full.
// 0bxx1xxxxx: Link to INT2
// 0bxxx11111: 32 samplesADXL375_SetRegisterValue(ADXL375_FIFO_CTL, 0xFF);        //
ADXL375_SetRegisterValue(ADXL375_POWER_CTL, 0x08);        // Go!
(void)ADXL375_GetRegisterValue(ADXL375_ACT_SHOCK_STATUS);
(void)ADXL375_GetRegisterValue(ADXL375_INT_SOURCE);       // clear INT1!

And here's the signals involved

If I'm running at 3200 ODR with a 32 samples FIFO depth I expect to get the interrupt INT1 exactly every 10ms in order to read the 32 samples into the FIFO. However I see a time of 9.6335ms. It seems I have 1 sample lost but I don't why. Could someone confirm this and how should I do to fix it?

regards,
gaston

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  • +1
    •  Analog Employees 
    on May 14, 2018 7:21 PM

    I've looked up our characterization data. The internal clock is factory trimmed at 25°C to be accurate within about ±2%. More than 99% of parts will be within 51Khz ±5%, which also applies to the ODR.

    Hope this helps.

Reply
  • +1
    •  Analog Employees 
    on May 14, 2018 7:21 PM

    I've looked up our characterization data. The internal clock is factory trimmed at 25°C to be accurate within about ±2%. More than 99% of parts will be within 51Khz ±5%, which also applies to the ODR.

    Hope this helps.

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