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Referring to ADXL362

Thread Summary

The user observed a 15% lower ODR than the nominal 25Hz setting in the FILTER_CTL register (Address 0x2C). The issue was assumed to be resolved offline or through a multi-part answer, and the thread is now closed. No specific solution was provided in the final answer.
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I see that ODR can be set in the FILTER_CTL register (Address 0x2C), and the device provides a discrete # of options for ODR. Setting to 25Hz, I'm seeing ~15% lower ODR than the nominal setting. Is this kind of drift normal/expected?