ADXL372 external synchronization

Hello Terumasa-san, 

For your question:

1:

Which  is the sample timing of internal ADC  based on  the EXT_SYNC or  internal clock?

Answer: The sampling of the internal ADC depends on the user selected ODR. Since you chose to use an EXT_SYNC signal, which then sets the ODR, the ADC sampling rate is now equal to the EXT_SYNC signal's frequency.

2

The relationship of the internal clock and external sync are asynchronou.

Is the acceleration data of ADXL372 interpolated 

as the sample timing of accleration data  equals the timing trrigered by EXT_SYNC?

Answer: As far as the datasheet is concerned, there is no mentioning of an interpolation of the acceleration data. 

3

Does below timing chart  describes  Data ready ?

If this is data ready,  this timing chart means that one data is lost.

Could you teach me why the data is lost ?

If there is the timing chart which indicates this reason, could you provide me of it ?

Answer: In the case of using an EXT_SYNC signal, the acceleration samples are produced every time the EXT_SYNC signal goes high. This means that it also sets the DATA_RDY bit every time a new valid data is available. Yes, that would mean that data for one cycle would be lost but still this may only happen as stated in the data sheet which means that it is only a possibility and may not happen at all times. This happens due to the asynchronous nature of the internal clock and external sync.

As the sample statement on the data sheet says "For example, if sending an external sync at a 2 kHz rate, all 3 axes (if enabled) are sampled in that 2 kHz window", with your customer's application using the same frequency of 2 kHz, this means that the acceleration data is sampled in the 2 kHz window. 

I hope that this has helped answer your questions.

Regards, 

JP

Hello Terumasa-san, 

For your question:

1:

Which  is the sample timing of internal ADC  based on  the EXT_SYNC or  internal clock?

Answer: The sampling of the internal ADC depends on the user selected ODR. Since you chose to use an EXT_SYNC signal, which then sets the ODR, the ADC sampling rate is now equal to the EXT_SYNC signal's frequency.

2

The relationship of the internal clock and external sync are asynchronou.

Is the acceleration data of ADXL372 interpolated 

as the sample timing of accleration data  equals the timing trrigered by EXT_SYNC?

Answer: As far as the datasheet is concerned, there is no mentioning of an interpolation of the acceleration data. 

3

Does below timing chart  describes  Data ready ?

If this is data ready,  this timing chart means that one data is lost.

Could you teach me why the data is lost ?

If there is the timing chart which indicates this reason, could you provide me of it ?

Answer: In the case of using an EXT_SYNC signal, the acceleration samples are produced every time the EXT_SYNC signal goes high. This means that it also sets the DATA_RDY bit every time a new valid data is available. Yes, that would mean that data for one cycle would be lost but still this may only happen as stated in the data sheet which means that it is only a possibility and may not happen at all times. This happens due to the asynchronous nature of the internal clock and external sync.

As the sample statement on the data sheet says "For example, if sending an external sync at a 2 kHz rate, all 3 axes (if enabled) are sampled in that 2 kHz window", with your customer's application using the same frequency of 2 kHz, this means that the acceleration data is sampled in the 2 kHz window. 

I hope that this has helped answer your questions.

Regards, 

JP