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ADXL372 external synchronization

Hello

Our customer will use ADXL372 at external sync (2000Hz) and internal clock (ODR=3200 Hz setting).

Datasheet rev.0 P24  "SYNCHRONIZED DATA SAMPLING" says below.

"

The EXT_SYNC is an active high signal. Due to the asynchronous
nature of the internal clock and external sync, there may be a
one ODR clock cycle difference between consecutive external sync
pulses. "

Question

What does one ODR clock cycle difference  mean ?

I think  that  ADXL372  outputs date at 1/3200 second after sync (every 1/2000 second )

when SYNC is 2000Hz and ODR setting is3200Hz (internal clock ).

Please let me know your advice how  "one ODR clock cycle difference" affects ADXL372 operation .

Regards,

Terumasa

Parents
  • Hello John.Tuazon-san,

    Thank you for your reply.

    I can not understand the meaning of one ODR clock cycle difference yet.

    Could you teach me your advice ?

    Question1

     I think  below as attachment slide1.

    Is my understanding correct ?

    ADXL372 starts internal sampling operation of ADC after SYNC  and RDY is set to 1 for 310us  .

    The operation ( internal sampling operation ?) in the period of Ta by next SYNC  is lost at next SYNC.

    So System ODR equals to  SYNC frequency.

    Question 2

    Does One ODR clock cycle difference  mean that  ADXL372 may not output  after SYNC ?

    ( I do not understand that  slide2 means)

    Coud you teach me your advice ?

    Regards,

    Terumasa

    reference.pptx
Reply
  • Hello John.Tuazon-san,

    Thank you for your reply.

    I can not understand the meaning of one ODR clock cycle difference yet.

    Could you teach me your advice ?

    Question1

     I think  below as attachment slide1.

    Is my understanding correct ?

    ADXL372 starts internal sampling operation of ADC after SYNC  and RDY is set to 1 for 310us  .

    The operation ( internal sampling operation ?) in the period of Ta by next SYNC  is lost at next SYNC.

    So System ODR equals to  SYNC frequency.

    Question 2

    Does One ODR clock cycle difference  mean that  ADXL372 may not output  after SYNC ?

    ( I do not understand that  slide2 means)

    Coud you teach me your advice ?

    Regards,

    Terumasa

    reference.pptx
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