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Hello

Our customer will use ADXL372 at external sync (2000Hz) and internal clock (ODR=3200 Hz setting).

Datasheet rev.0 P24  "SYNCHRONIZED DATA SAMPLING" says below.

"

The EXT_SYNC is an active high signal. Due to the asynchronous
nature of the internal clock and external sync, there may be a
one ODR clock cycle difference between consecutive external sync
pulses. "

Question

What does one ODR clock cycle difference  mean ?

I think  that  ADXL372  outputs date at 1/3200 second after sync (every 1/2000 second )

when SYNC is 2000Hz and ODR setting is3200Hz (internal clock ).

Regards,

Terumasa

• Hello - san,

From the datasheet, it is said that "The external sync sets the ODR of the system" . This would mean that the ODR of the system is equal to 2 kHz. The statement that there may be a one ODR clock cycle difference between consecutive external pulses refers to this:

Regards,

JP

• Hello John.Tuazon-san,

I can not understand the meaning of one ODR clock cycle difference yet.

Question1

I think  below as attachment slide1.

Is my understanding correct ?

ADXL372 starts internal sampling operation of ADC after SYNC  and RDY is set to 1 for 310us  .

The operation ( internal sampling operation ?) in the period of Ta by next SYNC  is lost at next SYNC.

So System ODR equals to  SYNC frequency.

Question 2

Does One ODR clock cycle difference  mean that  ADXL372 may not output  after SYNC ?

( I do not understand that  slide2 means)

Regards,

Terumasa

reference.pptx
• Hi -san,

What I have meant to say is that if you have an external sync, the ODR would not be equal to 3200 Hz even though that you have it in the internal clock.

The 3200 Hz internal clock is disregarded while the EXT_SYNC signal is the one that dictates the ODR.

Referring to the second slide, it would mean that the next EXT_SYNC pulse after the first one would be delayed by one ODR clock cycle. This means to say that it would be delayed by one period.

Regards,

JP

• Hi John-san,

Can I ask  below question ?

1:

Which  is the sample timing of internal ADC  based on  the EXT_SYNC or  internal clock?

2

The relationship of the internal clock and external sync are asynchronou.

Is the acceleration data of ADXL372 interpolated

as the sample timing of accleration data  equals the timing trrigered by EXT_SYNC?

3

Does below timing chart  describes  Data ready ?

If this is data ready,  this timing chart means that one data is lost.

Could you teach me why the data is lost ?

If there is the timing chart which indicates this reason, could you provide me of it ?

Regards,

Terumasa

• Hello -san,

1:

Which  is the sample timing of internal ADC  based on  the EXT_SYNC or  internal clock?

Answer: The sampling of the internal ADC depends on the user selected ODR. Since you chose to use an EXT_SYNC signal, which then sets the ODR, the ADC sampling rate is now equal to the EXT_SYNC signal's frequency.

2

The relationship of the internal clock and external sync are asynchronou.

Is the acceleration data of ADXL372 interpolated

as the sample timing of accleration data  equals the timing trrigered by EXT_SYNC?

Answer: As far as the datasheet is concerned, there is no mentioning of an interpolation of the acceleration data.

3

Does below timing chart  describes  Data ready ?

If this is data ready,  this timing chart means that one data is lost.

Could you teach me why the data is lost ?

If there is the timing chart which indicates this reason, could you provide me of it ?

Answer: In the case of using an EXT_SYNC signal, the acceleration samples are produced every time the EXT_SYNC signal goes high. This means that it also sets the DATA_RDY bit every time a new valid data is available. Yes, that would mean that data for one cycle would be lost but still this may only happen as stated in the data sheet which means that it is only a possibility and may not happen at all times. This happens due to the asynchronous nature of the internal clock and external sync.

As the sample statement on the data sheet says "For example, if sending an external sync at a 2 kHz rate, all 3 axes (if enabled) are sampled in that 2 kHz window", with your customer's application using the same frequency of 2 kHz, this means that the acceleration data is sampled in the 2 kHz window.

Regards,

JP